发表了主题帖： 【microchip PolarFire SoC FPGA 套件】⑩作品提交：毫米波雷达探测小车

【microchip PolarFire SoC FPGA 套件】⑨RISC-V SoC驱动FPGA软核CoreUART https://bbs.eeworld.com.cn/thread-1311327-1-1.html   书接上回，通过RISC-V SoC驱动FPGA软核CoreUART成功，接下来就来到本次体验的重点：雷达波小车   通过雷达波探测距离，进而控制小车运行。 程序流程大致如图所示：                 首先深入介绍下毫米波雷达。 本次使用的毫米波雷达模块是：海凌科LD2450     LD2450是一款24G毫米波雷达系列中的运动目标跟踪/目标存在检测传感器模组，包含极简化24GHz雷达传感器硬件和智能算法固件。 传感器硬件由AloT毫米波雷达芯片、高性能一发两收微带天线和低成本MCU及外围辅助电路组成。智能算法固件采用FMCW波形和雷达芯片专有的先进信号处理技术。支持串口输出检测数据，即插即用，可灵活应用于不同的智能场景和终端产品。 好了，言归正传，我们先了解下毫米波雷达的串口协议。   默认5V，其实3.3V也是支持的，在图中右上方有3.3V引脚。 模块IO输出电平为3.3V。串口默认波特率256000， 1停止位，无奇偶校验位。（本例改为波特率115200） 该模块一上电，就会以0.2秒的间隔发送 30Byte的探测码。 如： AA FF 03 00 0E 03 B1 86 10 00 40 01 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 55 CC 其中有价值的信息就是 0E 03 B1 86 这一串，分别表示了X轴坐标，Y轴坐标。     当然原始数据需要经过运算， 得到X轴坐标，Y轴坐标，距离就好办了。 公式如图：   核心的串口解码程序如下：   if(UART_APB_NO_ERROR == UART_get_rx_status(&g_uart))     {         rx_size=UART_get_rx(&g_uart, rx_buf, 1);   //每次接收1字节         if(rx_size == 1)         {             rx_size=0;             if(rx_buf[0] == 0xAA || i>1)    //如果捕捉到0xAA进入解码程序             {rx_buf1= rx_buf[0];                 i++;                 if(i==9)                 {                   //UART_send(&g_uart, rx_buf1,sizeof(rx_buf1));                   x1[0] = rx_buf1[5] + (rx_buf1[6] *256);   //X数据                   y1[0] = rx_buf1[7] + (rx_buf1[8] *256);   //Y数据                   if(rx_buf1[6] & 0x80)                     {                       x1[0]-= 0x8000;                     }                     y1[0]-= 0x8000;                     distance0 = sqrt(pow(x1[0],2) + pow(y1[0],2)); //距离计算       下面是此前解码毫米波雷达的过程：   毫米波雷达串口输出的原始数据（每10ms发送一次）   距离计算结果：       接下来介绍小车电机驱动： 本例使用4个电机的小车，也算是四驱车了        4路电机的驱动使用 L9110 H桥4路电机驱动模块：       驱动也毕竟简单：               与Polarfire Soc FPGA Discovery Kit的硬件连接如下：                   程序方面：   电机控制对应的端口初始化：          MSS_GPIO_config(GPIO2_LO, MSS_GPIO_8, MSS_GPIO_OUTPUT_MODE);  //A1        MSS_GPIO_config(GPIO2_LO, MSS_GPIO_9, MSS_GPIO_OUTPUT_MODE);  //A2        MSS_GPIO_config(GPIO2_LO, MSS_GPIO_11, MSS_GPIO_OUTPUT_MODE); //B1        MSS_GPIO_config(GPIO2_LO, MSS_GPIO_12, MSS_GPIO_OUTPUT_MODE); //B2        MSS_GPIO_config(GPIO2_LO, MSS_GPIO_14, MSS_GPIO_OUTPUT_MODE); //C1        MSS_GPIO_config(GPIO2_LO, MSS_GPIO_16, MSS_GPIO_OUTPUT_MODE); //C2        MSS_GPIO_config(GPIO2_LO, MSS_GPIO_15, MSS_GPIO_OUTPUT_MODE); //D1        MSS_GPIO_config(GPIO1_LO, MSS_GPIO_13, MSS_GPIO_OUTPUT_MODE); //D2   IO输出（前进）：      MSS_GPIO_set_output(GPIO2_LO, MSS_GPIO_8, 0);   //A1右后轮     MSS_GPIO_set_output(GPIO2_LO, MSS_GPIO_9, 1);     MSS_GPIO_set_output(GPIO2_LO, MSS_GPIO_11, 0);  //A2左后轮     MSS_GPIO_set_output(GPIO2_LO, MSS_GPIO_12, 1);     MSS_GPIO_set_output(GPIO2_LO, MSS_GPIO_14, 0);  //A3右前轮     MSS_GPIO_set_output(GPIO2_LO, MSS_GPIO_16, 1);     MSS_GPIO_set_output(GPIO2_LO, MSS_GPIO_15, 0);  //A4左前轮     MSS_GPIO_set_output(GPIO2_LO, MSS_GPIO_13, 1);       distance0 = sqrt(pow(x1[0],2) + pow(y1[0],2)); //距离计算                     if(distance0<600)      //关闭右侧2个轮子，启动左侧2个轮子，小车右转。                     {                      MSS_GPIO_set_output(GPIO2_LO, MSS_GPIO_8, 0);   //右后轮 停车                      MSS_GPIO_set_output(GPIO2_LO, MSS_GPIO_9, 0);                      MSS_GPIO_set_output(GPIO2_LO, MSS_GPIO_14, 0);   //右前轮 停车                      MSS_GPIO_set_output(GPIO2_LO, MSS_GPIO_16, 0);                      MSS_GPIO_set_output(GPIO2_LO, MSS_GPIO_11, 0);  //左后轮 启动                     MSS_GPIO_set_output(GPIO2_LO, MSS_GPIO_12, 1);                      MSS_GPIO_set_output(GPIO2_LO, MSS_GPIO_15, 0);  //左前轮 启动                      MSS_GPIO_set_output(GPIO2_LO, MSS_GPIO_13, 1);                     }                     else                                                                               //前进                     {                         MSS_GPIO_set_output(GPIO2_LO, MSS_GPIO_8, 0);   //右后轮                         MSS_GPIO_set_output(GPIO2_LO, MSS_GPIO_9, 1);                         MSS_GPIO_set_output(GPIO2_LO, MSS_GPIO_11, 0);  //左后轮                         MSS_GPIO_set_output(GPIO2_LO, MSS_GPIO_12, 1);                         MSS_GPIO_set_output(GPIO2_LO, MSS_GPIO_14, 0);  //右前轮                         MSS_GPIO_set_output(GPIO2_LO, MSS_GPIO_16, 1);                         MSS_GPIO_set_output(GPIO2_LO, MSS_GPIO_15, 0);  //左前轮                         MSS_GPIO_set_output(GPIO2_LO, MSS_GPIO_13, 1);                     }                  // UART_send(&g_uart, distance,sizeof(distance));                   itoa(distance0,distance,10);                                            //把距离数据转化为String                   UART_polled_tx_string(&g_uart,distance);                    //串口输出距离数据                   UART_polled_tx_string(&g_uart,"\n");                   //UART_send(&g_uart, y1,sizeof(x1));                   i=0;           测试结果：感应灵敏，转向精准，不过最后还是无情地撞墙了    [localvideo]e7e5efdc35651c3ab95d6310e65cfce7[/localvideo]       全部程序见以下，本次的体验就到这里。         /******************************************************************************* * Copyright 2019-2022 Microchip FPGA Embedded Systems Solutions. * * SPDX-License-Identifier: MIT * * Application code running on U54_1 * * PolarFire SoC MSS GPIO interrupt example project */ #include <stdio.h> #include <string.h> #include "math.h" #include "stdlib.h" #include "mpfs_hal/mss_hal.h" #include "drivers/mss/mss_gpio/mss_gpio.h" #include "drivers/mss/mss_mmuart/mss_uart.h" #include "drivers/fpga_ip/CoreUARTapb/core_uart_apb.h" #include "inc/uart_mapping.h" extern struct mss_uart_instance* p_uartmap_u54_1; /****************************************************************************** * Instruction message. These message will be displayed on the UART terminal when the program starts. *****************************************************************************/ uint8_t g_message2[] = "\r\n\r\n\r\n **** PolarFire SoC MSS GPIO example ****\r\n\r\n\r\n\ This program is running on u54_1.\r\n\r\n\ Observe the LEDs blinking. LEDs toggle every time the SYSTICK timer expires\r\n\ \r\n\ Press 1 to generate interrupt on GPIO2 pin 30.\r\n\ Press 2 to generate interrupt on GPIO2 pin 31.\r\n\ Press 3 to generate interrupt on F2M_0 signal.\r\n"; #define RX_BUFF_SIZE 64U uint8_t g_rx_buff[RX_BUFF_SIZE] = {0}; volatile uint8_t g_rx_size = 0U; uint32_t getBaudValue(uint32_t baud_rate); UART_instance_t g_uart; /* Main function for the hart1(U54 processor). * Application code running on hart1 is placed here. * On Icicle kit, apart from the UART menu, you can also use push button * switches to generate GPIO interrupts. The mapping is as follows * push button SW1 - MSS_INT_F2M[0] * push button SW2 - GPIO2_30 * push button SW3 - GPIO2_31 */ void delay1(void) {uint64_t j; for(j=0;j<1000000;j++); } void u54_1(void) { uint64_t mcycle_start = 0U; uint64_t mcycle_end = 0U; uint64_t delta_mcycle = 0U; uint64_t hartid = read_csr(mhartid); uint8_t cnt = 16U, int_num = 0U; /* Clear pending software interrupt in case there was any. * Enable only the software interrupt so that the E51 core can bring this * core out of WFI by raising a software interrupt In case of external, * bootloader not present */ clear_soft_interrupt(); set_csr(mie, MIP_MSIP); #if (IMAGE_LOADED_BY_BOOTLOADER == 0) /*Put this hart into WFI.*/ do { __asm("wfi"); }while(0 == (read_csr(mip) & MIP_MSIP)); /* The hart is out of WFI, clear the SW interrupt. Hear onwards Application * can enable and use any interrupts as required */ clear_soft_interrupt(); #endif PLIC_init(); __enable_irq(); /* Reset the peripherals turn on the clocks */ (void)mss_config_clk_rst(MSS_PERIPH_MMUART_U54_1, (uint8_t) MPFS_HAL_FIRST_HART, PERIPHERAL_ON); (void)mss_config_clk_rst(MSS_PERIPH_MMUART_U54_2, (uint8_t) MPFS_HAL_FIRST_HART, PERIPHERAL_ON); (void)mss_config_clk_rst(MSS_PERIPH_MMUART_U54_3, (uint8_t) MPFS_HAL_FIRST_HART, PERIPHERAL_ON); (void)mss_config_clk_rst(MSS_PERIPH_GPIO0, (uint8_t) MPFS_HAL_FIRST_HART, PERIPHERAL_ON); (void)mss_config_clk_rst(MSS_PERIPH_GPIO1, (uint8_t) MPFS_HAL_FIRST_HART, PERIPHERAL_ON); (void)mss_config_clk_rst(MSS_PERIPH_GPIO2, (uint8_t) MPFS_HAL_FIRST_HART, PERIPHERAL_ON); (void)mss_config_clk_rst(MSS_PERIPH_CFM, (uint8_t) MPFS_HAL_FIRST_HART, PERIPHERAL_ON); /* mmuart1 initialization */ MSS_UART_init( p_uartmap_u54_1, MSS_UART_115200_BAUD, MSS_UART_DATA_8_BITS | MSS_UART_NO_PARITY | MSS_UART_ONE_STOP_BIT); MSS_UART_polled_tx_string(p_uartmap_u54_1, g_message2 ); UART_init(&g_uart, 0x40000300,26, (DATA_8_BITS | NO_PARITY)); //总线地址0x40000300 26对应115200 //UART_polled_tx_string(&g_uart, "Hello World~\r\n"); mcycle_start = readmcycle(); /* Configure Systick. The tick rate is configured in mss_sw_config.h */ SysTick_Config(); /* Making sure that the GPIO2 interrupts are routed to the PLIC instead of * GPIO0 and GPIO1. * Please see the mss_gpio.h for more description on how GPIO interrupts * are routed to the PLIC */ SYSREG->GPIO_INTERRUPT_FAB_CR = 0xFFFFFFFFUL; PLIC_SetPriority_Threshold(0); for (int_num = 0u; int_num <= GPIO2_NON_DIRECT_PLIC; int_num++) { PLIC_SetPriority(GPIO0_BIT0_or_GPIO2_BIT0_PLIC_0 + int_num, 2u); } MSS_GPIO_init(GPIO2_LO); MSS_GPIO_config(GPIO2_LO, MSS_GPIO_8, MSS_GPIO_OUTPUT_MODE); //A1 MSS_GPIO_config(GPIO2_LO, MSS_GPIO_9, MSS_GPIO_OUTPUT_MODE); //A2 MSS_GPIO_config(GPIO2_LO, MSS_GPIO_11, MSS_GPIO_OUTPUT_MODE); //B1 MSS_GPIO_config(GPIO2_LO, MSS_GPIO_12, MSS_GPIO_OUTPUT_MODE); //B2 MSS_GPIO_config(GPIO2_LO, MSS_GPIO_14, MSS_GPIO_OUTPUT_MODE); //C1 MSS_GPIO_config(GPIO2_LO, MSS_GPIO_16, MSS_GPIO_OUTPUT_MODE); //C2 MSS_GPIO_config(GPIO2_LO, MSS_GPIO_15, MSS_GPIO_OUTPUT_MODE); //D1 MSS_GPIO_config(GPIO1_LO, MSS_GPIO_13, MSS_GPIO_OUTPUT_MODE); //D2 MSS_GPIO_config(GPIO2_LO, MSS_GPIO_17, MSS_GPIO_OUTPUT_MODE); //LED1 MSS_GPIO_config(GPIO2_LO, MSS_GPIO_18, MSS_GPIO_OUTPUT_MODE); //LED2 MSS_GPIO_config(GPIO2_LO, MSS_GPIO_19, MSS_GPIO_OUTPUT_MODE); //LED3 MSS_GPIO_config(GPIO2_LO, MSS_GPIO_20, MSS_GPIO_OUTPUT_MODE); //LED4 MSS_GPIO_config(GPIO2_LO, MSS_GPIO_21, MSS_GPIO_OUTPUT_MODE); //LED5 MSS_GPIO_config(GPIO2_LO, MSS_GPIO_22, MSS_GPIO_OUTPUT_MODE); //LED6 MSS_GPIO_config(GPIO2_LO, MSS_GPIO_23, MSS_GPIO_OUTPUT_MODE); //LED7 MSS_GPIO_config(GPIO1_LO, MSS_GPIO_9, MSS_GPIO_OUTPUT_MODE); //LED8 MSS_GPIO_config(GPIO2_LO, MSS_GPIO_26, MSS_GPIO_OUTPUT_MODE); MSS_GPIO_config(GPIO2_LO, MSS_GPIO_27, MSS_GPIO_OUTPUT_MODE); MSS_GPIO_config(GPIO2_LO, MSS_GPIO_28, MSS_GPIO_OUTPUT_MODE); MSS_GPIO_config(GPIO2_LO, MSS_GPIO_30, MSS_GPIO_INPUT_MODE | MSS_GPIO_IRQ_LEVEL_HIGH); MSS_GPIO_config(GPIO2_LO, MSS_GPIO_31, MSS_GPIO_INPUT_MODE | MSS_GPIO_IRQ_LEVEL_HIGH); MSS_GPIO_set_outputs(GPIO2_LO, 0u); MSS_GPIO_set_output(GPIO2_LO, MSS_GPIO_8, 0); //A1右后轮 MSS_GPIO_set_output(GPIO2_LO, MSS_GPIO_9, 1); MSS_GPIO_set_output(GPIO2_LO, MSS_GPIO_11, 0); //A2左后轮 MSS_GPIO_set_output(GPIO2_LO, MSS_GPIO_12, 1); MSS_GPIO_set_output(GPIO2_LO, MSS_GPIO_14, 0); //A3右前轮 MSS_GPIO_set_output(GPIO2_LO, MSS_GPIO_16, 1); MSS_GPIO_set_output(GPIO2_LO, MSS_GPIO_15, 0); //A4左前轮 MSS_GPIO_set_output(GPIO2_LO, MSS_GPIO_13, 1); MSS_GPIO_enable_irq(GPIO2_LO, MSS_GPIO_30); MSS_GPIO_enable_irq(GPIO2_LO, MSS_GPIO_31); PLIC_SetPriority(FABRIC_F2H_0_PLIC, 2); PLIC_EnableIRQ(FABRIC_F2H_0_PLIC); uint8_t rx_size = 0; uint8_t rx_size1 = 0; uint8_t i = 0; unsigned char rx_buf[1]; unsigned char rx_buf1[9]; uint16_t x1[1]; uint8_t x1h[1]; uint8_t x1l[1]; uint16_t y1[1]; uint8_t y1h[1]; uint8_t y1l[1]; uint16_t distance0; unsigned char distance[10]; //MSS_GPIO_set_output(GPIO2_LO, MSS_GPIO_18, 1u); //delay_us(); //MSS_GPIO_set_output(GPIO2_LO, MSS_GPIO_18, 0u); //UART_polled_tx_string(&g_uart, "Hello World~\r\n"); while(1) { if(UART_APB_NO_ERROR == UART_get_rx_status(&g_uart)) { rx_size=UART_get_rx(&g_uart, rx_buf, 1); //每次接收1字节 if(rx_size == 1) { rx_size=0; if(rx_buf[0] == 0xAA || i>1) //如果捕捉到0xAA进入解码程序 {rx_buf1[i]= rx_buf[0]; i++; if(i==9) { //UART_send(&g_uart, rx_buf1,sizeof(rx_buf1)); x1[0] = rx_buf1[5] + (rx_buf1[6] *256); y1[0] = rx_buf1[7] + (rx_buf1[8] *256); if(rx_buf1[6] & 0x80) { x1[0]-= 0x8000; } y1[0]-= 0x8000; distance0 = sqrt(pow(x1[0],2) + pow(y1[0],2)); //距离计算 if(distance0<600) { MSS_GPIO_set_output(GPIO2_LO, MSS_GPIO_8, 0); //右后轮 停车 MSS_GPIO_set_output(GPIO2_LO, MSS_GPIO_9, 0); MSS_GPIO_set_output(GPIO2_LO, MSS_GPIO_14, 0); //右前轮 停车 MSS_GPIO_set_output(GPIO2_LO, MSS_GPIO_16, 0); MSS_GPIO_set_output(GPIO2_LO, MSS_GPIO_11, 0); //左后轮 启动 MSS_GPIO_set_output(GPIO2_LO, MSS_GPIO_12, 1); MSS_GPIO_set_output(GPIO2_LO, MSS_GPIO_15, 0); //左前轮 启动 MSS_GPIO_set_output(GPIO2_LO, MSS_GPIO_13, 1); } else { MSS_GPIO_set_output(GPIO2_LO, MSS_GPIO_8, 0); //右后轮 MSS_GPIO_set_output(GPIO2_LO, MSS_GPIO_9, 1); MSS_GPIO_set_output(GPIO2_LO, MSS_GPIO_11, 0); //左后轮 MSS_GPIO_set_output(GPIO2_LO, MSS_GPIO_12, 1); MSS_GPIO_set_output(GPIO2_LO, MSS_GPIO_14, 0); //右前轮 MSS_GPIO_set_output(GPIO2_LO, MSS_GPIO_16, 1); MSS_GPIO_set_output(GPIO2_LO, MSS_GPIO_15, 0); //左前轮 MSS_GPIO_set_output(GPIO2_LO, MSS_GPIO_13, 1); } // UART_send(&g_uart, distance,sizeof(distance)); itoa(distance0,distance,10); UART_polled_tx_string(&g_uart,distance); UART_polled_tx_string(&g_uart,"\n"); //UART_send(&g_uart, y1,sizeof(x1)); i=0; } } } } } //UART_send(&g_uart, rx_buf, rx_size); //MSS_UART_polled_tx(p_uartmap_u54_1, rx_buf, sizeof(rx_buf)); //MSS_UART_polled_tx_string(p_uartmap_u54_1, rx_buf); //MSS_GPIO_set_output(GPIO2_LO, MSS_GPIO_17, 1u); //delay_us(); //MSS_GPIO_set_output(GPIO2_LO, MSS_GPIO_17, 0u); //MSS_GPIO_set_output(GPIO2_LO, MSS_GPIO_19, 1u); //delay_us(); //MSS_GPIO_set_output(GPIO2_LO, MSS_GPIO_19, 0u); //MSS_GPIO_set_output(GPIO2_LO, MSS_GPIO_20, 1u); //delay_us(); // MSS_GPIO_set_output(GPIO2_LO, MSS_GPIO_20, 0u); //MSS_GPIO_set_output(GPIO2_LO, MSS_GPIO_21, 1u); //delay_us(); //MSS_GPIO_set_output(GPIO2_LO, MSS_GPIO_21, 0u); //MSS_GPIO_set_output(GPIO2_LO, MSS_GPIO_22, 1u); // delay_us(); //MSS_GPIO_set_output(GPIO2_LO, MSS_GPIO_22, 0u); //MSS_GPIO_set_output(GPIO2_LO, MSS_GPIO_23, 1u); //delay_us(); //MSS_GPIO_set_output(GPIO2_LO, MSS_GPIO_23, 0u); //MSS_GPIO_set_output(GPIO1_LO, MSS_GPIO_9, 1u); //delay_us(); //MSS_GPIO_set_output(GPIO1_LO, MSS_GPIO_9, 0u); } /* g_rx_size = MSS_UART_get_rx(p_uartmap_u54_1, g_rx_buff, sizeof(g_rx_buff)); if (g_rx_size > 0u) { switch (g_rx_buff[0u]) { case '1': MSS_GPIO_set_output(GPIO2_LO, MSS_GPIO_26, 1u); MSS_GPIO_set_output(GPIO1_LO, MSS_GPIO_9, 1u); //LED8 ON break; case '2': MSS_GPIO_set_output(GPIO2_LO, MSS_GPIO_27, 1u); break; case '3': MSS_GPIO_set_output(GPIO2_LO, MSS_GPIO_28, 1); break; default: /* Echo the characters received from the terminal */ /* MSS_UART_polled_tx_string(p_uartmap_u54_1, g_rx_buff ); } g_rx_size = 0; } */ /* GPIO interrupt handlers */ uint8_t gpio1_bit16_or_gpio2_bit30_plic_30_IRQHandler(void) { MSS_UART_polled_tx_string(p_uartmap_u54_1, "gpio2_pin 30 Interrupt\r\n"); MSS_GPIO_set_outputs(GPIO2_LO, 0u); MSS_GPIO_clear_irq(GPIO2_LO, MSS_GPIO_30); return EXT_IRQ_KEEP_ENABLED; } uint8_t gpio1_bit17_or_gpio2_bit31_plic_31_IRQHandler(void) { MSS_UART_polled_tx_string(p_uartmap_u54_1, "gpio2_pin 31 Interrupt\r\n" ); MSS_GPIO_set_outputs(GPIO2_LO, 0u); MSS_GPIO_clear_irq(GPIO2_LO, MSS_GPIO_31); return EXT_IRQ_KEEP_ENABLED; } uint8_t fabric_f2h_0_plic_IRQHandler(void) { MSS_UART_polled_tx_string(p_uartmap_u54_1, "f2h_0 interrupt\r\n" ); MSS_GPIO_set_outputs(GPIO2_LO, 0u); return EXT_IRQ_KEEP_ENABLED; } void SysTick_Handler_h1_IRQHandler(void) { uint32_t hart_id = read_csr(mhartid); static volatile uint8_t value = 0u; if (1u == hart_id) { if(0u == value) { value = 0x01u; } else { value = 0x00u; } MSS_GPIO_set_output(GPIO2_LO, MSS_GPIO_17, value); } }  

回复了主题帖： 【microchip PolarFire SoC FPGA 套件】⑧回到原点：SoftConsole点亮RISC-V跑马灯

nmg 发表于 2025-4-11 15:54 英文技术文档阅读能力up 没办法被逼的，Microchip的东西用的人太少了，搜中文资料几乎没有，被迫去啃github  

回复了主题帖： 【microchip PolarFire SoC FPGA 套件】⑨RISC-V SoC驱动FPGA软核CoreUART

1112121 发表于 2025-4-9 15:21 会出以太网教程吗 有可能 ，毕竟Linux都跑起来了 

回复了主题帖： 【PolarFire SoC FPGA Discovery 套件】通过EMMC启动Linux?

dfjs 发表于 2025-4-6 23:30 用SD卡我也测试成功了，我想通过EMMC存储介质来试一下 这个板子上没有EMMC硬件，只能通过SD启动Linux。

回复了主题帖： 【PolarFire SoC FPGA Discovery 套件】通过EMMC启动Linux?

哥们，请看我2025-3-24发的贴子： 【microchip PolarFire SoC FPGA 套件】⑥见到曙光：烧录并启动Linux https://bbs.eeworld.com.cn/thread-1310222-1-1.html

发表了主题帖： 【microchip PolarFire SoC FPGA 套件】⑨RISC-V SoC驱动FPGA软核CoreUART

  书接上回： https://bbs.eeworld.com.cn/thread-1311160-1-1.html   SoftConsole点亮RISC-V跑马灯后，我就在想，RISC-V SoC核现在理论上可以驱动板上的所有内设、外设。不仅包括RISC-V SoC核自身所挂的，还包括FPGA的外设。 要不就先从最简单的串口UART开始吧。   上一帖我们已经驱动成功RISC-V SoC自带的UART：对应于USB转的虚拟串口。   那怎么驱动开发板上的物理串口呢，以便跟我们后面要用到的雷达波或者GPS模块通讯？   于是我看到了开发板上的 mikroBUS Connector 上第一排对应的RX TX引脚，没错就是他了。         那要如何驱动这个mikroBUS上的UART串口呢，经过长时间的摸索，终于搞定了。 我们再温习下这个图，也就是polarfire-soc-discovery-kit-reference-design 在我的前贴已经说过，他是本系统的核心，相当于电脑的BIOS，最先烧录到CPU中，后续的开发都基于前述BIOS搭好的物理框架。 https://bbs.eeworld.com.cn/thread-1310056-1-1.html       在这个架构图上可以看到。 MSS（RISC-V SoC）直属的3个串口：MMUART0、MMUART1、MMUART4都被FTDI UART Bridge（电脑端虚拟串口）给占用了。     mikroBUS UART隶属于FPGA核（CORE_UART），通过FIC_3总线与MSS（RISC-V SoC）核通讯。     注意上面标注的地址：0x40000300，这个很重要，后面编程会用到，他对应UART的总线地址。   那什么是CORE_UART呢，简单来说他是一个FPGA模拟出来的软核。 MSS的UART，也就是我们常规MCU的串口。他的管脚是固定的不能分配，而FPGA的UART是可以用软核自由指定的。   如果想使用普通的管脚作为串口来，就需要使用到CoreUARTapb这个IP核了，它是使用FPGA逻辑部分实现的一个串口IP，MCU硬核可以通过CoreAPB3总线访问，通过对MCU的编程，可以方便的实现串口数据的发送和接收，可以扩展出多个串口。本节演示CoreAPB3总线IP的使用，以挂载CoreUARTapb为例，后续的CorePWM，CoreGPIO，CoreSPI，CoreI2C等都是挂载在的CoreAPB3总线上。   回到正题，明白了coreUART的作用，接下来我们就通过Softconsole编程驱动吧！     在mpfs-gpio-interrupt这个例程中可以看到。 Platform/drivers下面由2个子目录， 1个是fpga_ip也就是FPGA下挂的软核，可以指定任意引脚，通过FPGA软核实现对应的功能，如CoreUARTapb，CorePWM，CoreGPIO，CoreSPI，CoreI2C等。 1个是mss也就是RISC-V SoC下挂的硬核，就是常规的MCU引脚已经定好不能改变，通过MCU寄存器实现对应的功能，如MSS_mmuart，MSS_GPIO等。     microchip在这个例程中，已经汇总了驱动程序。 无论是通过MSS驱动的CoreGPIO、CoreUART等 还是通过FPGA_IP软核驱动的GPIO、UART等，都有对应HAL库函数，类似当下非常流行的STM32 HAL库函数。 要使用什么功能，直接去.h .c里找就行了，如图的core_uart_apb.h中对于串口初始化的定义。 UART_init(&g_uart, COREUARTAPB0_BASE_ADDR,                    BAUD_VALUE_57600, (DATA_8_BITS | EVEN_PARITY));   接下来我们正式开始CoreUART的编程。 首先，我们准备好硬件。 使用一个USB转串口工具，接线至mikroBUS Connector 上第一排对应的RX TX引脚。 （TX对TX，RX对RX，不要接反了）   在u54_1.c中添加以下程序（总共4句话，非常简单）   #include "drivers/fpga_ip/CoreUARTapb/core_uart_apb.h"    //引用HAL函数 UART_instance_t g_uart;  //定义CoreUART UART_init(&g_uart, 0x40000300,26, (DATA_8_BITS | EVEN_PARITY));   //初始化CoreUART，定义波特率、位数、奇偶校验等。 UART_polled_tx_string(&g_uart, "Hello World~\r\n");   //发送字符串   对于UART_init的详细解读如下：  * @param this_uart   The this_uart parameter is a pointer to the   *                    UART_instance_t structure, which holds all data regarding   *                    this instance of the CoreUARTapb. This pointer is used to  *                    identify the target CoreUARTapb hardware instance in   *                    subsequent calls to the CoreUARTapb functions.  * @param base_addr   The base_address parameter is the base address in the   *                    processor's memory map for the registers of the   *                    CoreUARTapb instance being initialized.  * @param baud_value  The baud_value parameter selects the baud rate for the  *                    UART. The baud value is calculated from the frequency of  *                    the system clock in hertz and the desired baud rate using  *                    the following equation:                        *                    baud_value = (clock / (baud_rate * 16)) - 1.      *                    The baud_value parameter must be a value in the range 0   *                    to 8191 (or 0x0000 to 0x1FFF).  * @param line_config This parameter is the line configuration, specifies the   *                    bit length and parity settings. This is the logical OR of:  *                     - DATA_7_BITS  *                     - DATA_8_BITS  *                     - NO_PARITY  *                     - EVEN_PARITY  *                     - ODD_PARITY    *                    For example, 8 bits even parity would be specified as   *                    (DATA_8_BITS | EVEN_PARITY).    波特率baud_value = (clock / (baud_rate * 16)) - 1 我们看下图，给到FIC外设（包括）的时钟是50MHZ，也就是50000000，50000000/115200*16-1=26     以上程序编译运行后，电脑端的USB转串口（我电脑是COM7），就可以收到字符串了，说明CoreUART驱动成功。       [localvideo]2821a76cda208c7df37079418059343b[/localvideo]   本次分享就到这里。   u54_1.c完整程序如下： /******************************************************************************* * Copyright 2019-2022 Microchip FPGA Embedded Systems Solutions. * * SPDX-License-Identifier: MIT * * Application code running on U54_1 * * PolarFire SoC MSS GPIO interrupt example project */ #include <stdio.h> #include <string.h> #include "mpfs_hal/mss_hal.h" #include "drivers/mss/mss_gpio/mss_gpio.h" #include "drivers/mss/mss_mmuart/mss_uart.h" #include "drivers/fpga_ip/CoreUARTapb/core_uart_apb.h" #include "inc/uart_mapping.h" extern struct mss_uart_instance* p_uartmap_u54_1; /****************************************************************************** * Instruction message. These message will be displayed on the UART terminal when the program starts. *****************************************************************************/ uint8_t g_message2[] = "\r\n\r\n\r\n **** PolarFire SoC MSS GPIO example ****\r\n\r\n\r\n\ This program is running on u54_1.\r\n\r\n\ Observe the LEDs blinking. LEDs toggle every time the SYSTICK timer expires\r\n\ \r\n\ Press 1 to generate interrupt on GPIO2 pin 30.\r\n\ Press 2 to generate interrupt on GPIO2 pin 31.\r\n\ Press 3 to generate interrupt on F2M_0 signal.\r\n"; #define RX_BUFF_SIZE 64U uint8_t g_rx_buff[RX_BUFF_SIZE] = {0}; volatile uint8_t g_rx_size = 0U; uint32_t getBaudValue(uint32_t baud_rate); UART_instance_t g_uart; /* Main function for the hart1(U54 processor). * Application code running on hart1 is placed here. * On Icicle kit, apart from the UART menu, you can also use push button * switches to generate GPIO interrupts. The mapping is as follows * push button SW1 - MSS_INT_F2M[0] * push button SW2 - GPIO2_30 * push button SW3 - GPIO2_31 */ void delay_us() { int i; for(i=0;i<1000000;i++) i++; } void u54_1(void) { uint64_t mcycle_start = 0U; uint64_t mcycle_end = 0U; uint64_t delta_mcycle = 0U; uint64_t hartid = read_csr(mhartid); uint8_t cnt = 16U, int_num = 0U; /* Clear pending software interrupt in case there was any. * Enable only the software interrupt so that the E51 core can bring this * core out of WFI by raising a software interrupt In case of external, * bootloader not present */ clear_soft_interrupt(); set_csr(mie, MIP_MSIP); #if (IMAGE_LOADED_BY_BOOTLOADER == 0) /*Put this hart into WFI.*/ do { __asm("wfi"); }while(0 == (read_csr(mip) & MIP_MSIP)); /* The hart is out of WFI, clear the SW interrupt. Hear onwards Application * can enable and use any interrupts as required */ clear_soft_interrupt(); #endif PLIC_init(); __enable_irq(); /* Reset the peripherals turn on the clocks */ (void)mss_config_clk_rst(MSS_PERIPH_MMUART_U54_1, (uint8_t) MPFS_HAL_FIRST_HART, PERIPHERAL_ON); (void)mss_config_clk_rst(MSS_PERIPH_MMUART_U54_2, (uint8_t) MPFS_HAL_FIRST_HART, PERIPHERAL_ON); (void)mss_config_clk_rst(MSS_PERIPH_MMUART_U54_3, (uint8_t) MPFS_HAL_FIRST_HART, PERIPHERAL_ON); (void)mss_config_clk_rst(MSS_PERIPH_GPIO0, (uint8_t) MPFS_HAL_FIRST_HART, PERIPHERAL_ON); (void)mss_config_clk_rst(MSS_PERIPH_GPIO1, (uint8_t) MPFS_HAL_FIRST_HART, PERIPHERAL_ON); (void)mss_config_clk_rst(MSS_PERIPH_GPIO2, (uint8_t) MPFS_HAL_FIRST_HART, PERIPHERAL_ON); (void)mss_config_clk_rst(MSS_PERIPH_CFM, (uint8_t) MPFS_HAL_FIRST_HART, PERIPHERAL_ON); /* mmuart1 initialization */ MSS_UART_init( p_uartmap_u54_1, MSS_UART_115200_BAUD, MSS_UART_DATA_8_BITS | MSS_UART_NO_PARITY | MSS_UART_ONE_STOP_BIT); MSS_UART_polled_tx_string(p_uartmap_u54_1, g_message2 ); UART_init(&g_uart, 0x40000300,26, (DATA_8_BITS | EVEN_PARITY)); //0x40000300 UART_polled_tx_string(&g_uart, "Hello World~\r\n"); mcycle_start = readmcycle(); /* Configure Systick. The tick rate is configured in mss_sw_config.h */ SysTick_Config(); /* Making sure that the GPIO2 interrupts are routed to the PLIC instead of * GPIO0 and GPIO1. * Please see the mss_gpio.h for more description on how GPIO interrupts * are routed to the PLIC */ SYSREG->GPIO_INTERRUPT_FAB_CR = 0xFFFFFFFFUL; PLIC_SetPriority_Threshold(0); for (int_num = 0u; int_num <= GPIO2_NON_DIRECT_PLIC; int_num++) { PLIC_SetPriority(GPIO0_BIT0_or_GPIO2_BIT0_PLIC_0 + int_num, 2u); } MSS_GPIO_init(GPIO2_LO); MSS_GPIO_config(GPIO2_LO, MSS_GPIO_17, MSS_GPIO_OUTPUT_MODE); //LED1 MSS_GPIO_config(GPIO2_LO, MSS_GPIO_18, MSS_GPIO_OUTPUT_MODE); //LED2 MSS_GPIO_config(GPIO2_LO, MSS_GPIO_19, MSS_GPIO_OUTPUT_MODE); //LED3 MSS_GPIO_config(GPIO2_LO, MSS_GPIO_20, MSS_GPIO_OUTPUT_MODE); //LED4 MSS_GPIO_config(GPIO2_LO, MSS_GPIO_21, MSS_GPIO_OUTPUT_MODE); //LED5 MSS_GPIO_config(GPIO2_LO, MSS_GPIO_22, MSS_GPIO_OUTPUT_MODE); //LED6 MSS_GPIO_config(GPIO2_LO, MSS_GPIO_23, MSS_GPIO_OUTPUT_MODE); //LED7 MSS_GPIO_config(GPIO1_LO, MSS_GPIO_9, MSS_GPIO_OUTPUT_MODE); //LED8 MSS_GPIO_config(GPIO2_LO, MSS_GPIO_26, MSS_GPIO_OUTPUT_MODE); MSS_GPIO_config(GPIO2_LO, MSS_GPIO_27, MSS_GPIO_OUTPUT_MODE); MSS_GPIO_config(GPIO2_LO, MSS_GPIO_28, MSS_GPIO_OUTPUT_MODE); MSS_GPIO_config(GPIO2_LO, MSS_GPIO_30, MSS_GPIO_INPUT_MODE | MSS_GPIO_IRQ_LEVEL_HIGH); MSS_GPIO_config(GPIO2_LO, MSS_GPIO_31, MSS_GPIO_INPUT_MODE | MSS_GPIO_IRQ_LEVEL_HIGH); MSS_GPIO_set_outputs(GPIO2_LO, 0u); MSS_GPIO_enable_irq(GPIO2_LO, MSS_GPIO_30); MSS_GPIO_enable_irq(GPIO2_LO, MSS_GPIO_31); PLIC_SetPriority(FABRIC_F2H_0_PLIC, 2); PLIC_EnableIRQ(FABRIC_F2H_0_PLIC); while (1u) { MSS_GPIO_set_output(GPIO2_LO, MSS_GPIO_18, 1u); delay_us(); MSS_GPIO_set_output(GPIO2_LO, MSS_GPIO_18, 0u); UART_polled_tx_string(&g_uart, "Hello World~\r\n"); //MSS_GPIO_set_output(GPIO2_LO, MSS_GPIO_17, 1u); delay_us(); //MSS_GPIO_set_output(GPIO2_LO, MSS_GPIO_17, 0u); //MSS_GPIO_set_output(GPIO2_LO, MSS_GPIO_19, 1u); //delay_us(); //MSS_GPIO_set_output(GPIO2_LO, MSS_GPIO_19, 0u); //MSS_GPIO_set_output(GPIO2_LO, MSS_GPIO_20, 1u); //delay_us(); // MSS_GPIO_set_output(GPIO2_LO, MSS_GPIO_20, 0u); //MSS_GPIO_set_output(GPIO2_LO, MSS_GPIO_21, 1u); //delay_us(); //MSS_GPIO_set_output(GPIO2_LO, MSS_GPIO_21, 0u); //MSS_GPIO_set_output(GPIO2_LO, MSS_GPIO_22, 1u); // delay_us(); //MSS_GPIO_set_output(GPIO2_LO, MSS_GPIO_22, 0u); //MSS_GPIO_set_output(GPIO2_LO, MSS_GPIO_23, 1u); //delay_us(); //MSS_GPIO_set_output(GPIO2_LO, MSS_GPIO_23, 0u); //MSS_GPIO_set_output(GPIO1_LO, MSS_GPIO_9, 1u); //delay_us(); //MSS_GPIO_set_output(GPIO1_LO, MSS_GPIO_9, 0u); /* g_rx_size = MSS_UART_get_rx(p_uartmap_u54_1, g_rx_buff, sizeof(g_rx_buff)); if (g_rx_size > 0u) { switch (g_rx_buff[0u]) { case '1': MSS_GPIO_set_output(GPIO2_LO, MSS_GPIO_26, 1u); MSS_GPIO_set_output(GPIO1_LO, MSS_GPIO_9, 1u); //LED8 ON break; case '2': MSS_GPIO_set_output(GPIO2_LO, MSS_GPIO_27, 1u); break; case '3': MSS_GPIO_set_output(GPIO2_LO, MSS_GPIO_28, 1); break; default: /* Echo the characters received from the terminal */ /* MSS_UART_polled_tx_string(p_uartmap_u54_1, g_rx_buff ); } g_rx_size = 0; } */ } } /* GPIO interrupt handlers */ uint8_t gpio1_bit16_or_gpio2_bit30_plic_30_IRQHandler(void) { MSS_UART_polled_tx_string(p_uartmap_u54_1, "gpio2_pin 30 Interrupt\r\n"); MSS_GPIO_set_outputs(GPIO2_LO, 0u); MSS_GPIO_clear_irq(GPIO2_LO, MSS_GPIO_30); return EXT_IRQ_KEEP_ENABLED; } uint8_t gpio1_bit17_or_gpio2_bit31_plic_31_IRQHandler(void) { MSS_UART_polled_tx_string(p_uartmap_u54_1, "gpio2_pin 31 Interrupt\r\n" ); MSS_GPIO_set_outputs(GPIO2_LO, 0u); MSS_GPIO_clear_irq(GPIO2_LO, MSS_GPIO_31); return EXT_IRQ_KEEP_ENABLED; } uint8_t fabric_f2h_0_plic_IRQHandler(void) { MSS_UART_polled_tx_string(p_uartmap_u54_1, "f2h_0 interrupt\r\n" ); MSS_GPIO_set_outputs(GPIO2_LO, 0u); return EXT_IRQ_KEEP_ENABLED; } void SysTick_Handler_h1_IRQHandler(void) { uint32_t hart_id = read_csr(mhartid); static volatile uint8_t value = 0u; if (1u == hart_id) { if(0u == value) { value = 0x01u; } else { value = 0x00u; } // MSS_GPIO_set_output(GPIO2_LO, MSS_GPIO_17, value); LED1 ON/OFF } }  

发表了主题帖： 【microchip PolarFire SoC FPGA 套件】⑧回到原点：SoftConsole点亮RISC-V跑马灯

【microchip PolarFire SoC FPGA 套件】④求助：如何通过FPGA驱动SoC GPIO？ - FPGA/CPLD - 电子工程世界-论坛 https://bbs.eeworld.com.cn/thread-1308660-1-1.html   【microchip PolarFire SoC FPGA 套件】⑤尝试通过SoftConsole启动RISC-V内核 - FPGA/CPLD - 电子工程世界-论坛 https://bbs.eeworld.com.cn/thread-1310056-1-1.html   我曾在论坛发帖求助，如何通过FPGA驱动SoC GPIO，并尝试通过SoftConsole启动RISC-V内核，但实际上都未真正成功驱动RISC-V SoC的 GPIO。 直到绕了很大的弯路，通过烧录Linux，在Linux下使用命令行驱动GPIO并跑通跑马灯。这等于将简单的问题复杂化了。 【microchip PolarFire SoC FPGA 套件】⑦不忘初心：在Linux下点个跑马灯 - FPGA/CPLD - 电子工程世界-论坛 https://bbs.eeworld.com.cn/thread-1310343-1-1.html 能不能用简单的代码（裸机）驱动GPIO并跑一个跑马灯呢？经过多天阅读官方文档及尝试，终于搞定！！！   步骤一：烧录polarfire-soc-discovery-kit-reference-design HSS（裸机和Linux的引导程序，类似BIOS） 下载地址：   https://github.com/polarfire-soc/polarfire-soc-discovery-kit-reference-design/releases/tag/v2024.06           步骤二：下载官方裸机例程 https://github.com/polarfire-soc/polarfire-soc-bare-metal-examples     本例即是 mpfs-gpio-interrupt 1.导入例程     2. 设置开发板型号       3.修改官方例程。   我们看下面这个图polarfire-soc-discovery-kit-reference-design，可以看到  LED[0:7]对应 GPIO_2_[17:23]，LED8对应GPIO_1_9 也就是说 LED1——GPIO2_17 LED2——GPIO2_18 LED3——GPIO2_19 LED4——GPIO2_20 LED5——GPIO2_21 LED6——GPIO2_22 LED7——GPIO2_23 LED8——GPIO1_9                 u54_1.c 这个就是启动后的第一个RISC-V核：   主要修改如下： 设置LED1-8对应的端口为输出模式：     MSS_GPIO_config(GPIO2_LO, MSS_GPIO_17, MSS_GPIO_OUTPUT_MODE); //LED1     MSS_GPIO_config(GPIO2_LO, MSS_GPIO_18, MSS_GPIO_OUTPUT_MODE); //LED2     MSS_GPIO_config(GPIO2_LO, MSS_GPIO_19, MSS_GPIO_OUTPUT_MODE); //LED3     MSS_GPIO_config(GPIO2_LO, MSS_GPIO_20, MSS_GPIO_OUTPUT_MODE); //LED4     MSS_GPIO_config(GPIO2_LO, MSS_GPIO_21, MSS_GPIO_OUTPUT_MODE); //LED5     MSS_GPIO_config(GPIO2_LO, MSS_GPIO_22, MSS_GPIO_OUTPUT_MODE); //LED6     MSS_GPIO_config(GPIO2_LO, MSS_GPIO_23, MSS_GPIO_OUTPUT_MODE); //LED7     MSS_GPIO_config(GPIO1_LO, MSS_GPIO_9, MSS_GPIO_OUTPUT_MODE);  //LED8   跑马灯主循环：   while (1u)     {         MSS_GPIO_set_output(GPIO2_LO, MSS_GPIO_17, 1u);         delay_us(10000000);         MSS_GPIO_set_output(GPIO2_LO, MSS_GPIO_17, 0u);         MSS_GPIO_set_output(GPIO2_LO, MSS_GPIO_18, 1u);         delay_us(10000000);         MSS_GPIO_set_output(GPIO2_LO, MSS_GPIO_18, 0u);         MSS_GPIO_set_output(GPIO2_LO, MSS_GPIO_19, 1u);         delay_us(10000000);         MSS_GPIO_set_output(GPIO2_LO, MSS_GPIO_19, 0u);         MSS_GPIO_set_output(GPIO2_LO, MSS_GPIO_20, 1u);         delay_us(10000000);         MSS_GPIO_set_output(GPIO2_LO, MSS_GPIO_20, 0u);         MSS_GPIO_set_output(GPIO2_LO, MSS_GPIO_21, 1u);         delay_us(10000000);         MSS_GPIO_set_output(GPIO2_LO, MSS_GPIO_21, 0u);         MSS_GPIO_set_output(GPIO2_LO, MSS_GPIO_22, 1u);         delay_us(10000000);         MSS_GPIO_set_output(GPIO2_LO, MSS_GPIO_22, 0u);         MSS_GPIO_set_output(GPIO2_LO, MSS_GPIO_23, 1u);         delay_us(10000000);         MSS_GPIO_set_output(GPIO2_LO, MSS_GPIO_23, 0u);         MSS_GPIO_set_output(GPIO1_LO, MSS_GPIO_9, 1u);         delay_us(10000000);         MSS_GPIO_set_output(GPIO1_LO, MSS_GPIO_9, 0u); }   e51.c如下：（e51 RISC-V监控核） /******************************************************************************* * Copyright 2019-2022 Microchip FPGA Embedded Systems Solutions. * * SPDX-License-Identifier: MIT * * Application code running on e51 * */ #include <stdio.h> #include <string.h> #include "mpfs_hal/mss_hal.h" #include "drivers/mss/mss_mmuart/mss_uart.h" #include "inc/uart_mapping.h" extern struct mss_uart_instance* p_uartmap_e51; volatile uint32_t count_sw_ints_h0 = 0U; const uint8_t g_info_string[] = " \r\n\r\n------------------------------------\ ---------------------------------\r\n\r\n\ Please observe UART1, as application is using UART1 as \ User-Interface\r\n\r\n--------------------------------\ -------------------------------------\r\n"; /* Main function for the hart0(e51 processor). * Application code running on hart0 is placed here */ void e51(void) { volatile uint32_t icount = 0U; uint64_t hartid = read_csr(mhartid); uint32_t pattern_offset = 12U; (void)mss_config_clk_rst(MSS_PERIPH_MMUART_E51, (uint8_t) MPFS_HAL_FIRST_HART, PERIPHERAL_ON); MSS_UART_init( p_uartmap_e51, MSS_UART_115200_BAUD, MSS_UART_DATA_8_BITS | MSS_UART_NO_PARITY | MSS_UART_ONE_STOP_BIT); MSS_UART_polled_tx_string(p_uartmap_e51, g_info_string); #if (IMAGE_LOADED_BY_BOOTLOADER == 0) /* Clear pending software interrupt in case there was any. */ clear_soft_interrupt(); set_csr(mie, MIP_MSIP); /* Raise software interrupt to wake hart 1 */ raise_soft_interrupt(1U); __enable_irq(); #endif while (1U) { icount++; if (0x100000U == icount) { icount = 0U; } } /* never return */ } /* hart0 software interrupt handler */ void Software_h0_IRQHandler(void) { uint64_t hart_id = read_csr(mhartid); count_sw_ints_h0++; }     u54_1.c如下：（u54 RISC-V应用核） /******************************************************************************* * Copyright 2019-2022 Microchip FPGA Embedded Systems Solutions. * * SPDX-License-Identifier: MIT * * Application code running on U54_1 * * PolarFire SoC MSS GPIO interrupt example project */ #include <stdio.h> #include <string.h> #include "mpfs_hal/mss_hal.h" #include "drivers/mss/mss_gpio/mss_gpio.h" #include "drivers/mss/mss_mmuart/mss_uart.h" #include "inc/uart_mapping.h" extern struct mss_uart_instance* p_uartmap_u54_1; /****************************************************************************** * Instruction message. These message will be displayed on the UART terminal when the program starts. *****************************************************************************/ uint8_t g_message2[] = "\r\n\r\n\r\n **** PolarFire SoC MSS GPIO example ****\r\n\r\n\r\n\ This program is running on u54_1.\r\n\r\n\ Observe the LEDs blinking. LEDs toggle every time the SYSTICK timer expires\r\n\ \r\n\ Press 1 to generate interrupt on GPIO2 pin 30.\r\n\ Press 2 to generate interrupt on GPIO2 pin 31.\r\n\ Press 3 to generate interrupt on F2M_0 signal.\r\n"; #define RX_BUFF_SIZE 64U uint8_t g_rx_buff[RX_BUFF_SIZE] = {0}; volatile uint8_t g_rx_size = 0U; /* Main function for the hart1(U54 processor). * Application code running on hart1 is placed here. * On Icicle kit, apart from the UART menu, you can also use push button * switches to generate GPIO interrupts. The mapping is as follows * push button SW1 - MSS_INT_F2M[0] * push button SW2 - GPIO2_30 * push button SW3 - GPIO2_31 */ delay_us(unsigned int num) { int i; for(i=0;i<num;i++) i++; } void u54_1(void) { uint64_t mcycle_start = 0U; uint64_t mcycle_end = 0U; uint64_t delta_mcycle = 0U; uint64_t hartid = read_csr(mhartid); uint8_t cnt = 16U, int_num = 0U; /* Clear pending software interrupt in case there was any. * Enable only the software interrupt so that the E51 core can bring this * core out of WFI by raising a software interrupt In case of external, * bootloader not present */ clear_soft_interrupt(); set_csr(mie, MIP_MSIP); #if (IMAGE_LOADED_BY_BOOTLOADER == 0) /*Put this hart into WFI.*/ do { __asm("wfi"); }while(0 == (read_csr(mip) & MIP_MSIP)); /* The hart is out of WFI, clear the SW interrupt. Hear onwards Application * can enable and use any interrupts as required */ clear_soft_interrupt(); #endif PLIC_init(); __enable_irq(); /* Reset the peripherals turn on the clocks */ (void)mss_config_clk_rst(MSS_PERIPH_MMUART_U54_1, (uint8_t) MPFS_HAL_FIRST_HART, PERIPHERAL_ON); (void)mss_config_clk_rst(MSS_PERIPH_MMUART_U54_2, (uint8_t) MPFS_HAL_FIRST_HART, PERIPHERAL_ON); (void)mss_config_clk_rst(MSS_PERIPH_MMUART_U54_3, (uint8_t) MPFS_HAL_FIRST_HART, PERIPHERAL_ON); (void)mss_config_clk_rst(MSS_PERIPH_GPIO0, (uint8_t) MPFS_HAL_FIRST_HART, PERIPHERAL_ON); (void)mss_config_clk_rst(MSS_PERIPH_GPIO1, (uint8_t) MPFS_HAL_FIRST_HART, PERIPHERAL_ON); (void)mss_config_clk_rst(MSS_PERIPH_GPIO2, (uint8_t) MPFS_HAL_FIRST_HART, PERIPHERAL_ON); (void)mss_config_clk_rst(MSS_PERIPH_CFM, (uint8_t) MPFS_HAL_FIRST_HART, PERIPHERAL_ON); /* mmuart1 initialization */ MSS_UART_init( p_uartmap_u54_1, MSS_UART_115200_BAUD, MSS_UART_DATA_8_BITS | MSS_UART_NO_PARITY | MSS_UART_ONE_STOP_BIT); MSS_UART_polled_tx_string(p_uartmap_u54_1, g_message2 ); mcycle_start = readmcycle(); /* Configure Systick. The tick rate is configured in mss_sw_config.h */ SysTick_Config(); /* Making sure that the GPIO2 interrupts are routed to the PLIC instead of * GPIO0 and GPIO1. * Please see the mss_gpio.h for more description on how GPIO interrupts * are routed to the PLIC */ SYSREG->GPIO_INTERRUPT_FAB_CR = 0xFFFFFFFFUL; PLIC_SetPriority_Threshold(0); for (int_num = 0u; int_num <= GPIO2_NON_DIRECT_PLIC; int_num++) { PLIC_SetPriority(GPIO0_BIT0_or_GPIO2_BIT0_PLIC_0 + int_num, 2u); } MSS_GPIO_init(GPIO2_LO); MSS_GPIO_config(GPIO2_LO, MSS_GPIO_17, MSS_GPIO_OUTPUT_MODE); //LED1 MSS_GPIO_config(GPIO2_LO, MSS_GPIO_18, MSS_GPIO_OUTPUT_MODE); //LED2 MSS_GPIO_config(GPIO2_LO, MSS_GPIO_19, MSS_GPIO_OUTPUT_MODE); //LED3 MSS_GPIO_config(GPIO2_LO, MSS_GPIO_20, MSS_GPIO_OUTPUT_MODE); //LED4 MSS_GPIO_config(GPIO2_LO, MSS_GPIO_21, MSS_GPIO_OUTPUT_MODE); //LED5 MSS_GPIO_config(GPIO2_LO, MSS_GPIO_22, MSS_GPIO_OUTPUT_MODE); //LED6 MSS_GPIO_config(GPIO2_LO, MSS_GPIO_23, MSS_GPIO_OUTPUT_MODE); //LED7 MSS_GPIO_config(GPIO1_LO, MSS_GPIO_9, MSS_GPIO_OUTPUT_MODE); //LED8 MSS_GPIO_config(GPIO2_LO, MSS_GPIO_26, MSS_GPIO_OUTPUT_MODE); MSS_GPIO_config(GPIO2_LO, MSS_GPIO_27, MSS_GPIO_OUTPUT_MODE); MSS_GPIO_config(GPIO2_LO, MSS_GPIO_28, MSS_GPIO_OUTPUT_MODE); MSS_GPIO_config(GPIO2_LO, MSS_GPIO_30, MSS_GPIO_INPUT_MODE | MSS_GPIO_IRQ_LEVEL_HIGH); MSS_GPIO_config(GPIO2_LO, MSS_GPIO_31, MSS_GPIO_INPUT_MODE | MSS_GPIO_IRQ_LEVEL_HIGH); MSS_GPIO_set_outputs(GPIO2_LO, 0u); MSS_GPIO_enable_irq(GPIO2_LO, MSS_GPIO_30); MSS_GPIO_enable_irq(GPIO2_LO, MSS_GPIO_31); PLIC_SetPriority(FABRIC_F2H_0_PLIC, 2); PLIC_EnableIRQ(FABRIC_F2H_0_PLIC); while (1u) { MSS_GPIO_set_output(GPIO2_LO, MSS_GPIO_17, 1u); delay_us(10000000); MSS_GPIO_set_output(GPIO2_LO, MSS_GPIO_17, 0u); MSS_GPIO_set_output(GPIO2_LO, MSS_GPIO_18, 1u); delay_us(10000000); MSS_GPIO_set_output(GPIO2_LO, MSS_GPIO_18, 0u); MSS_GPIO_set_output(GPIO2_LO, MSS_GPIO_19, 1u); delay_us(10000000); MSS_GPIO_set_output(GPIO2_LO, MSS_GPIO_19, 0u); MSS_GPIO_set_output(GPIO2_LO, MSS_GPIO_20, 1u); delay_us(10000000); MSS_GPIO_set_output(GPIO2_LO, MSS_GPIO_20, 0u); MSS_GPIO_set_output(GPIO2_LO, MSS_GPIO_21, 1u); delay_us(10000000); MSS_GPIO_set_output(GPIO2_LO, MSS_GPIO_21, 0u); MSS_GPIO_set_output(GPIO2_LO, MSS_GPIO_22, 1u); delay_us(10000000); MSS_GPIO_set_output(GPIO2_LO, MSS_GPIO_22, 0u); MSS_GPIO_set_output(GPIO2_LO, MSS_GPIO_23, 1u); delay_us(10000000); MSS_GPIO_set_output(GPIO2_LO, MSS_GPIO_23, 0u); MSS_GPIO_set_output(GPIO1_LO, MSS_GPIO_9, 1u); delay_us(10000000); MSS_GPIO_set_output(GPIO1_LO, MSS_GPIO_9, 0u); /* g_rx_size = MSS_UART_get_rx(p_uartmap_u54_1, g_rx_buff, sizeof(g_rx_buff)); if (g_rx_size > 0u) { switch (g_rx_buff[0u]) { case '1': MSS_GPIO_set_output(GPIO2_LO, MSS_GPIO_26, 1u); MSS_GPIO_set_output(GPIO1_LO, MSS_GPIO_9, 1u); //LED8 ON break; case '2': MSS_GPIO_set_output(GPIO2_LO, MSS_GPIO_27, 1u); break; case '3': MSS_GPIO_set_output(GPIO2_LO, MSS_GPIO_28, 1); break; default: /* Echo the characters received from the terminal */ /* MSS_UART_polled_tx_string(p_uartmap_u54_1, g_rx_buff ); } g_rx_size = 0; } */ } } /* GPIO interrupt handlers */ uint8_t gpio1_bit16_or_gpio2_bit30_plic_30_IRQHandler(void) { MSS_UART_polled_tx_string(p_uartmap_u54_1, "gpio2_pin 30 Interrupt\r\n"); MSS_GPIO_set_outputs(GPIO2_LO, 0u); MSS_GPIO_clear_irq(GPIO2_LO, MSS_GPIO_30); return EXT_IRQ_KEEP_ENABLED; } uint8_t gpio1_bit17_or_gpio2_bit31_plic_31_IRQHandler(void) { MSS_UART_polled_tx_string(p_uartmap_u54_1, "gpio2_pin 31 Interrupt\r\n" ); MSS_GPIO_set_outputs(GPIO2_LO, 0u); MSS_GPIO_clear_irq(GPIO2_LO, MSS_GPIO_31); return EXT_IRQ_KEEP_ENABLED; } uint8_t fabric_f2h_0_plic_IRQHandler(void) { MSS_UART_polled_tx_string(p_uartmap_u54_1, "f2h_0 interrupt\r\n" ); MSS_GPIO_set_outputs(GPIO2_LO, 0u); return EXT_IRQ_KEEP_ENABLED; } void SysTick_Handler_h1_IRQHandler(void) { uint32_t hart_id = read_csr(mhartid); static volatile uint8_t value = 0u; if (1u == hart_id) { if(0u == value) { value = 0x01u; } else { value = 0x00u; } // MSS_GPIO_set_output(GPIO2_LO, MSS_GPIO_17, value); LED1 ON/OFF } }       4. 编译，下载调试：         启动程序       第一个串口（e51 RISC-V监控核）：     第二个串口（u54 RISC-V应用核）       运行如下：       [localvideo]321942195517d6ed880ee8098372dc48[/localvideo]       本次分享就到这里。    

回复了主题帖： >>征集 | 晒电机控制痛点与难题，一起寻求最优解！

电机控制控制要同时调控速度、转矩、电流多个参数，难度较大，PID调参更是难上加难，好不容易调顺了，换个负载又得重来。现在流行智能算法，但搞机器学习训练模型，没点算力根本玩不转，期待更先进更便利的解决方案。

回复了主题帖： 【microchip PolarFire SoC FPGA 套件】④求助：如何通过FPGA驱动SoC GPIO？

经过半个月摸索，终于自己琢磨出办法来了，就是烧录Linux操作系统，并利用microchip写好的驱动，来驱动SoC GPIO。 详见： https://m.eeworld.com.cn/bbs_thread-1310343-1-1.html

发表了主题帖： 【microchip PolarFire SoC FPGA 套件】⑦不忘初心：在Linux下点个跑马灯

本帖最后由 cc1989summer 于 2025-3-25 22:28 编辑 https://bbs.eeworld.com.cn/thread-1310222-1-1.html   书接上回，我们在Polar fire Discovery板子上烧录了个基于命令行的linux。 那烧录玩后，拿这个Linux有啥用呢，不如先点个灯吧。   还记得在这篇里面有说LED8是挂在RISC-V SOC上的，用FPGA难以直接驱动。 https://bbs.eeworld.com.cn/thread-1308660-1-1.html   那么现在在Linux下，办法就有了。 输入密码root进入Linux系统后，我们来到/sys/class/目录。如图看到了很多熟悉的面孔，什么GPIO、LED、SPI、I2C等等，原来是microchip帮忙我们写好了驱动。     来到/sys/class/leds/目录，我们看到了Led1~Led8   点亮LED1： echo 1 > /sys/class/leds/led1/brightness 熄灭LED1： echo 0 > /sys/class/leds/led1/brightness   延时1秒 sleep 1 有这几个命令，我们就可以运行个跑马灯啦！   echo 1 > /sys/class/leds/led1/brightness&& sleep 1&& echo 1 > /sys/class/leds/led2/brightness&& sleep 1&& echo 1 > /sys/class/leds/led3/brightness&& sleep 1&& echo 1 > /sys/class/leds/led4/brightness&& sleep 1&& echo 1 > /sys/class/leds/led5/brightness&& sleep 1&& echo 1 > /sys/class/leds/led6/brightness&& sleep 1&& echo 1 > /sys/class/leds/led7/brightness&& sleep 1&& echo 1 > /sys/class/leds/led8/brightness&& sleep 1&& echo 0 > /sys/class/leds/led1/brightness&& sleep 1&& echo 0 > /sys/class/leds/led2/brightness&& sleep 1&& echo 0 > /sys/class/leds/led3/brightness&& sleep 1&& echo 0 > /sys/class/leds/led4/brightness&& sleep 1&& echo 0 > /sys/class/leds/led5/brightness&& sleep 1&& echo 0 > /sys/class/leds/led6/brightness&& sleep 1&& echo 0 > /sys/class/leds/led7/brightness&& sleep 1&& echo 0 > /sys/class/leds/led8/brightness&& sleep 1   直接把上述命令复制在命令行，按Enter就可以运行了。             [localvideo]764bdeb5d4f2842880fdfa1d616d98a9[/localvideo]   本次分享就到这里，更多功能后续再探索吧！

回复了主题帖： 【microchip PolarFire SoC FPGA 套件】⑥见到曙光：烧录并启动Linux

jobszheng5 发表于 2025-3-25 09:53 这系统就算启动起来了！ 鼓掌 嘿嘿，也是费了不少精力。

发表了主题帖： 【microchip PolarFire SoC FPGA 套件】⑥见到曙光：烧录并启动Linux

https://bbs.eeworld.com.cn/thread-1310056-1-1.html 书接上回，我们烧录了polarfire-soc-discovery-kit-reference-design 这本质上是一个HSS（Hart Software Services ），说通俗点有点像我们电脑上的BIOS，是一段小程序，负责把SD或者Flash上存放的Linux系统加载到RAM中运行。         本文要实现烧录并启动Linux，就要： 1.烧录这个HSS程序到开发板，这个步骤可以看到串口信息（本开发板对应的第1个串口） 2.烧录Linux系统到SD卡 3.把SD卡插上开发板，并通过串口与之交互（本开发板对应的第2个串口）   参见：https://github.com/polarfire-soc/polarfire-soc-documentation/blob/master/reference-designs-fpga-and-development-kits/updating-linux-in-mpfs-kit.md   需要用到的软件如下图：       MPFS_DISCOVERY.zip就是上面提到的HSS程序 下载地址：   https://github.com/polarfire-soc/polarfire-soc-discovery-kit-reference-design/releases/tag/v2024.06       core-image-minimal-dev-mpfs-disco-kit-20241010180946.rootfs.wic 就是裁剪版Linux 下载地址：   https://github.com/polarfire-soc/meta-polarfire-soc-yocto-bsp/releases       注意选对型号，并且下载下来后要解压，烧录的是解压出来的文件（793MB）。       还要用到2个工具。   第一个就是烧录HSS的软件：FPExpress（Libero自带的软件） 第二个就是烧录Linux到SD卡的工具：usbimager  下载地址：https://bztsrc.gitlab.io/usbimager/       具体步骤如下： 1.烧录这个HSS程序到开发板，这个步骤可以看到串口信息（本开发板对应的第1个串口）               烧录完成后就可以查看串口信息了：           2.烧录Linux系统到SD卡（读卡器）   烧录完的SD卡。     3.把SD卡插上开发板，并通过串口与之交互（本开发板对应的第2个串口）   串口1（HSS）：   HSS: decompressing from eNVM to L2 Scratch ... Passed [0.43187] wdog_service monitoring [u54_1] [u54_2] [u54_3] [u54_4] [0.50826] beu_service :: [init] -> [monitoring] [0.57032] Initializing Mi-V IHC [0.61424] u54 State Change: [Idle] [Idle] [Idle] [Idle] [0.69540] loop 1 took 6363798 ticks max 6363798 ticks) [0.76510] Initializing IPI Queues 3304 bytes @ a0288f0)... [0.753680] loop 3 took 402049484 ticks max 402049484 ticks) [0.761128] Initializing PMPs [0.765233] PolarFireR) SoC Hart Software Services HSS) - version 0.99.41-v2024.06 MPFS HAL version 2.3.102 / DDR Driver version 0.4.024 / Mi-V IHC version 0.1.1 / BOARD=mpfs-disco-kit c) Copyright 2017-2022 Microchip FPGA Embedded Systems Solutions. incorporating OpenSBI - version 1.2 c) Copyright 2019-2022 Western Digital Corporation. [0.800274] Build ID: 8c4c2f2ca49f8236d079f86da5e4e2bcec883c13 [0.807817] Built with the following tools: - riscv64-unknown-elf-gcc xPack GNU RISC-V Embedded GCC Microsemi SoftConsole build), 64-bit) 8.3.0 - GNU ld ) 2.35.1 [0.825672] Serial Number: da216c02d0de4e7714c690563971928f00000000000000000000000000000000000000000000000000000000000000000000 [0.839612] Segment Configuration: Cached: SEG0_0: offset 0x0080000000, physical DDR 0x00000000 Cached: SEG0_1: offset 0x1000000000, physical DDR 0x00000000 Non-cached: SEG1_2: offset 0x00c0000000, physical DDR 0x00000000 Non-cached: SEG1_3: offset 0x1400000000, physical DDR 0x00000000 Non-cached WCB: SEG1_4: offset 0x00d0000000, physical DDR 0x00000000 Non-cached WCB: SEG1_5: offset 0x1800000000, physical DDR 0x00000000 [0.884583] L2 Cache Configuration: L2-Scratchpad: 4 ways 512 KiB) L2-Cache: 8 ways 1024 KiB) L2-LIM: 4 ways 512 KiB) [0.900528] DESIGNID: MPFS_DISCOVERY_KIT [0.905971] DESIGNVER: 0000 [0.910172] BACKLEVEL: 0000 [0.914373] startup_service :: [init] -> [boot] [0.920484] ipi_poll_service :: [Init] -> [Monitoring] Press a key to enter CLI, ESC to skip Timeout in 1 second .. [3.897802] CLI boot interrupt timeout [3.902767] loop 280057 took 606532057 ticks max 606532057 ticks) [3.910692] Initializing Boot Image ... [3.915752] Trying to get boot image via MMC ... [3.921672] Attempting to select SDCARD ... Passed [3.951922] Preparing to copy from MMC to DDR ... [3.958128] Validated GPT Header ... [3.996164] Validated GPT Partition Entries ... [4.02387] Boot Partition found at index 1 [4.07873] Attempting to read image header 1632 bytes) ... [4.15563] Copying 744976 bytes to 0x103fc00000 [4.52653] MMC: Boot Image registered ... [4.57974] Boot image set name: "PolarFire-SoC-HSS::U-Boot" [4.64944] healthmon_service :: [init] -> [monitoring] [4.71723] boot_serviceu54_1) :: [Init] -> [SetupPMP] [4.78502] boot_serviceu54_2) :: [Init] -> [SetupPMP] [4.85281] boot_serviceu54_3) :: [Init] -> [SetupPMP] [4.92060] boot_serviceu54_4) :: [Init] -> [SetupPMP] >> [4.99126] boot_serviceu54_1)::Registering domain "u-boot.bin" hart mask 0x1e) [4.108101] boot_serviceu54_1) :: [SetupPMP] -> [SetupPMPComplete] [4.116121] boot_serviceu54_2) :: [SetupPMP] -> [SetupPMPComplete] [4.124142] boot_serviceu54_3) :: [SetupPMP] -> [SetupPMPComplete] [4.132162] boot_serviceu54_4) :: [SetupPMP] -> [SetupPMPComplete] [4.140182] u54 State Change: [Booting] [Booting] [Booting] [Booting] [4.149539] boot_serviceu54_1) :: [SetupPMPComplete] -> [ZeroInit] [4.157560] boot_serviceu54_2) :: [SetupPMPComplete] -> [ZeroInit] [4.165580] boot_serviceu54_3) :: [SetupPMPComplete] -> [ZeroInit] [4.173600] boot_serviceu54_4) :: [SetupPMPComplete] -> [ZeroInit] [4.181620] boot_serviceu54_1) :: [ZeroInit] -> [Download] [4.188877] boot_serviceu54_2) :: [ZeroInit] -> [Download] [4.196133] boot_serviceu54_3) :: [ZeroInit] -> [Download] [4.203390] boot_serviceu54_4) :: [ZeroInit] -> [Download] [4.210646] boot_serviceu54_1)::Processing boot image: "u-boot.bin" [4.218476] boot_serviceu54_2) :: [Download] -> [Complete] [4.225732] boot_serviceu54_3) :: [Download] -> [Complete] [4.232989] boot_serviceu54_4) :: [Download] -> [Complete] [4.300120] boot_serviceu54_1) :: [Download] -> [OpenSBIInit] [4.307663] boot_serviceu54_1)::Registering domain "u-boot.bin" hart mask 0x1e) [4.316733] boot_serviceu54_1) :: [OpenSBIInit] -> [Wait] [4.325231] boot_serviceu54_1) :: [Wait] -> [Complete] [4.380418] u54 State Change: [SBIHartInit] [Booting] [Booting] [Booting] [4.425103] boot_serviceu54_1) :: [Complete] -> [Idle] [4.438088] boot_serviceu54_2) :: [Complete] -> [Idle] [4.457566] boot_serviceu54_3) :: [Complete] -> [Idle] [4.475039] boot_serviceu54_4) :: [Complete] -> [Idle] [4.571188] u54 State Change: [Running] [SBIWaitForColdboot] [SBIWaitForColdboot] [SBIWaitForColdboot] [5.00578] SYSREG:PLL_STATUS_SR not equal to 0x707 0x727) [5.08790] SYSREG:MAINTENANCE_INT_SR changed since last read 0xf080) [5.18051] SYSREG:DLL_STATUS_SR changed since last read 0xf0017) [5.26931] IOSCB_PLL:pll_sw_0:PLL_CTRL changed since last read 0x1) [10.712721] u54 State Change: [Running] [Running] [SBIWaitForColdboot] [SBIWaitForColdboot] [10.742233] u54 State Change: [Running] [Running] [Running] [SBIWaitForColdboot] [10.770279] u54 State Change: [Running] [Running] [Running] [Running]     串口2（Linux）           输入密码root就可以登陆linux了.   DDR training ... Passed ( 3129 ms) [3.219540] DDR-Lo size is 32 MiB [3.224218] DDR-Hi size is 888 MiB OpenSBI v1.2 ____ _____ ____ _____ / __ \ / ____| _ \_ _| | | | |_ __ ___ _ __ | (___ | |_) || | | | | | '_ \ / _ \ '_ \ \___ \| _ < | | | |__| | |_) | __/ | | |____) | |_) || |_ \____/| .__/ \___|_| |_|_____/|____/_____| | | |_| Platform Name : Microchip PolarFire(R) SoC Platform Features : medeleg Platform HART Count : 5 Platform IPI Device : aclint-mswi Platform Timer Device : aclint-mtimer @ 1000000Hz Platform Console Device : mmuart Platform HSM Device : mpfs_hsm Platform PMU Device : --- Platform Reboot Device : mpfs_reset Platform Shutdown Device : mpfs_reset Firmware Base : 0xa000000 Firmware Size : 127 KB Runtime SBI Version : 1.0 Domain0 Name : root Domain0 Boot HART : 1 Domain0 HARTs : 1,2,3,4 Domain0 Region00 : 0x0000000002008000-0x000000000200bfff (I) Domain0 Region01 : 0x0000000002000000-0x0000000002007fff (I) Domain0 Region02 : 0x000000000a000000-0x000000000a01ffff () Domain0 Region03 : 0x0000000000000000-0xffffffffffffffff (R,W,X) Domain0 Next Address : 0x0000000080200000 Domain0 Next Arg1 : 0x0000000000000000 Domain0 Next Mode : S-mode Domain0 SysReset : yes Domain1 Name : u-boot.bin Domain1 Boot HART : 1 Domain1 HARTs : 1*,2*,3*,4* Domain1 Region00 : 0x000000000a000000-0x000000000a01ffff () Domain1 Region01 : 0x0000000000000000-0xffffffffffffffff (R,W,X) Domain1 Next Address : 0x0000000080200000 Domain1 Next Arg1 : 0x0000000000000000 Domain1 Next Mode : S-mode Domain1 SysReset : yes Boot HART ID : 1 Boot HART Domain : u-boot.bin Boot HART Priv Version : v1.10 Boot HART Base ISA : rv64imafdc Boot HART ISA Extensions : none Boot HART PMP Count : 16 Boot HART PMP Granularity : 4 Boot HART PMP Address Bits: 36 Boot HART MHPM Count : 2 Boot HART MIDELEG : 0x0000000000000222 Boot HART MEDELEG : 0x000000000000b109 U-Boot 2023.07.02-linux4microchip+fpga-2024.09 (Oct 08 2024 - 09:54:00 +0000) CPU: rv64imafdc Model: Microchip PolarFire-SoC Discovery Kit DRAM: 1 GiB (effective 1.8 GiB) Core: 48 devices, 10 uclasses, devicetree: separate MMC: mmc@20008000: 0 Loading Environment from FAT... OK In: serial@20106000 Out: serial@20106000 Err: serial@20106000 Net: eth0: ethernet@20110000 Hit any key to stop autoboot: 0 switch to partitions #0, OK mmc0 is current device Scanning mmc 0:1... Found U-Boot script /boot.scr 431 bytes read in 27 ms (14.6 KiB/s) ## Executing script at 8e000000 5319372 bytes read in 258 ms (19.7 MiB/s) ## Loading kernel from FIT Image at 8e000000 ... Using 'conf-microchip_mpfs-disco-kit.dtb' configuration Trying 'kernel-1' kernel subimage Description: Linux kernel Type: Kernel Image Compression: gzip compressed Data Start: 0x8e0000fc Data Size: 5297354 Bytes = 5.1 MiB Architecture: RISC-V OS: Linux Load Address: 0x80200000 Entry Point: 0x80200000 Hash algo: sha256 Hash value: 26e89203488fc914baa289732da4e618290091958cc14a1ec9af5e6b927fea4b Verifying Hash Integrity ... sha256+ OK ## Loading fdt from FIT Image at 8e000000 ... Using 'conf-microchip_mpfs-disco-kit.dtb' configuration Trying 'fdt-microchip_mpfs-disco-kit.dtb' fdt subimage Description: Flattened Device Tree blob Type: Flat Device Tree Compression: uncompressed Data Start: 0x8e50d6e8 Data Size: 20028 Bytes = 19.6 KiB Architecture: RISC-V Load Address: 0x8a000000 Hash algo: sha256 Hash value: 3acfef217aeaeb815ac79ea084d7eb933b68781c53ca00636221aa2539190057 Verifying Hash Integrity ... sha256+ OK Loading fdt from 0x8e50d6e8 to 0x8a000000 Booting using the fdt blob at 0x8a000000 Working FDT set to 8a000000 Uncompressing Kernel Image Using Device Tree in place at 000000008a000000, end 000000008a007e3b Working FDT set to 8a000000 Starting kernel ... [ 0.000000] Linux version 6.6.51-linux4microchip+fpga-2024.09-g56d7964a57cd (oe-user@oe-host) (riscv64-oe-linux-gcc (GCC) 11.4.0, GNU ld (GNU Binutils) 2.38.20220708) #1 SMP Wed Oct 9 11:00:43 UTC 2024 [ 0.000000] Machine model: Microchip PolarFire-SoC Discovery Kit [ 0.000000] SBI specification v1.0 detected [ 0.000000] SBI implementation ID=0x8 Version=0x10002 [ 0.000000] SBI TIME extension detected [ 0.000000] SBI IPI extension detected [ 0.000000] SBI RFENCE extension detected [ 0.000000] SBI SRST extension detected [ 0.000000] efi: UEFI not found. [ 0.000000] Reserved memory: created DMA memory pool at 0x00000000c4000000, size 64 MiB [ 0.000000] OF: reserved mem: initialized node non-cached-low-buffer, compatible id shared-dma-pool [ 0.000000] OF: reserved mem: 0x00000000c4000000..0x00000000c7ffffff (65536 KiB) nomap non-reusable non-cached-low-buffer [ 0.000000] Reserved memory: created DMA memory pool at 0x0000001412000000, size 256 MiB [ 0.000000] OF: reserved mem: initialized node non-cached-high-buffer, compatible id shared-dma-pool [ 0.000000] OF: reserved mem: 0x0000001412000000..0x0000001421ffffff (262144 KiB) nomap non-reusable non-cached-high-buffer [ 0.000000] OF: reserved mem: 0x0000000084000000..0x0000000087ffffff (65536 KiB) nomap non-reusable region[url=home.php?mod=space&uid=444176]@84000000[/url] [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000088000000, size 32 MiB [ 0.000000] OF: reserved mem: initialized node buffer@88000000, compatible id shared-dma-pool [ 0.000000] OF: reserved mem: 0x0000000088000000..0x0000000089ffffff (32768 KiB) nomap non-reusable buffer@88000000 [ 0.000000] Reserved memory: created DMA memory pool at 0x00000000c8000000, size 32 MiB [ 0.000000] OF: reserved mem: initialized node buffer@c8000000, compatible id shared-dma-pool [ 0.000000] OF: reserved mem: 0x00000000c8000000..0x00000000c9ffffff (32768 KiB) nomap non-reusable buffer@c8000000 [ 0.000000] Reserved memory: created DMA memory pool at 0x00000000d8000000, size 32 MiB [ 0.000000] OF: reserved mem: initialized node buffer@d8000000, compatible id shared-dma-pool [ 0.000000] OF: reserved mem: 0x00000000d8000000..0x00000000d9ffffff (32768 KiB) nomap non-reusable buffer@d8000000 [ 0.000000] Reserved memory: created DMA memory pool at 0x000000103fc00000, size 2 MiB [ 0.000000] OF: reserved mem: initialized node hss-buffer@103fc00000, compatible id shared-dma-pool [ 0.000000] OF: reserved mem: 0x000000103fc00000..0x000000103fdfffff (2048 KiB) nomap non-reusable hss-buffer@103fc00000 [ 0.000000] Zone ranges: [ 0.000000] DMA32 [mem 0x0000000080000000-0x00000000ffffffff] [ 0.000000] Normal [mem 0x0000000100000000-0x0000001421ffffff] [ 0.000000] Movable zone start for each node [ 0.000000] Early memory node ranges [ 0.000000] node 0: [mem 0x0000000080000000-0x0000000083ffffff] [ 0.000000] node 0: [mem 0x000000008a000000-0x0000000091ffffff] [ 0.000000] node 0: [mem 0x00000000c4000000-0x00000000c9ffffff] [ 0.000000] node 0: [mem 0x0000001022000000-0x000000103fbfffff] [ 0.000000] node 0: [mem 0x000000103fc00000-0x000000103fdfffff] [ 0.000000] node 0: [mem 0x000000103fe00000-0x000000103fffffff] [ 0.000000] node 0: [mem 0x0000001412000000-0x0000001421ffffff] [ 0.000000] Initmem setup node 0 [mem 0x0000000080000000-0x0000001421ffffff] [ 0.000000] On node 0, zone DMA32: 24576 pages in unavailable ranges [ 0.000000] On node 0, zone DMA32: 40960 pages in unavailable ranges [ 0.000000] On node 0, zone Normal: 32768 pages in unavailable ranges [ 0.000000] On node 0, zone Normal: 8192 pages in unavailable ranges [ 0.000000] On node 0, zone Normal: 24576 pages in unavailable ranges [ 0.000000] SBI HSM extension detected [ 0.000000] CPU with hartid=0 is not available [ 0.000000] riscv: base ISA extensions acdfim [ 0.000000] riscv: ELF capabilities acdfim [ 0.000000] percpu: Embedded 18 pages/cpu s35880 r8192 d29656 u73728 [ 0.000000] Kernel command line: earlycon=sbi root=/dev/mmcblk0p3 rootwait uio_pdrv_genirq.of_id=generic-uio [ 0.000000] Dentry cache hash table entries: 131072 (order: 8, 1048576 bytes, linear) [ 0.000000] Inode-cache hash table entries: 65536 (order: 7, 524288 bytes, linear) [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 258560 [ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off [ 0.000000] software IO TLB: area num 4. [ 0.000000] software IO TLB: mapped [mem 0x000000008e000000-0x0000000092000000] (64MB) [ 0.000000] Memory: 559376K/1048576K available (6160K kernel code, 4823K rwdata, 4096K rodata, 2157K init, 377K bss, 489200K reserved, 0K cma-reserved) [ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=4, Nodes=1 [ 0.000000] rcu: Hierarchical RCU implementation. [ 0.000000] rcu: RCU event tracing is enabled. [ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=64 to nr_cpu_ids=4. [ 0.000000] Tracing variant of Tasks RCU enabled. [ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies. [ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=4 [ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0 [ 0.000000] riscv-intc: 64 local interrupts mapped [ 0.000000] plic: interrupt-controller@c000000: mapped 186 interrupts with 4 handlers for 9 contexts. [ 0.000000] riscv: providing IPIs using SBI IPI extension [ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention. [ 0.000000] clocksource: riscv_clocksource: mask: 0xffffffffffffffff max_cycles: 0x1d854df40, max_idle_ns: 3526361616960 ns [ 0.000003] sched_clock: 64 bits at 1000kHz, resolution 1000ns, wraps every 2199023255500ns [ 0.000403] Console: colour dummy device 80x25 [ 0.000427] printk: console [tty0] enabled [ 0.002177] Calibrating delay loop (skipped), value calculated using timer frequency.. 2.00 BogoMIPS (lpj=4000) [ 0.002246] pid_max: default: 32768 minimum: 301 [ 0.002598] Mount-cache hash table entries: 2048 (order: 2, 16384 bytes, linear) [ 0.002729] Mountpoint-cache hash table entries: 2048 (order: 2, 16384 bytes, linear) [ 0.005057] CPU node for /cpus/cpu@0 exist but the possible cpu range is :0-3 [ 0.008263] RCU Tasks Trace: Setting shift to 2 and lim to 1 rcu_task_cb_adjust=1. [ 0.008645] riscv: ELF compat mode unsupported [ 0.008665] ASID allocator disabled (0 bits) [ 0.009081] rcu: Hierarchical SRCU implementation. [ 0.009120] rcu: Max phase no-delay instances is 1000. [ 0.009849] EFI services will not be available. [ 0.010951] smp: Bringing up secondary CPUs ... [ 0.040295] cpu1: Ratio of byte access time to unaligned word access is 0.01, unaligned accesses are slow [ 0.068365] cpu2: Ratio of byte access time to unaligned word access is 0.01, unaligned accesses are slow [ 0.096457] cpu3: Ratio of byte access time to unaligned word access is 0.01, unaligned accesses are slow [ 0.096748] smp: Brought up 1 node, 4 CPUs [ 0.099642] devtmpfs: initialized [ 0.107720] DMA: default coherent area is set [ 0.107781] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns [ 0.107851] futex hash table entries: 1024 (order: 4, 65536 bytes, linear) [ 0.110711] NET: Registered PF_NETLINK/PF_ROUTE protocol family [ 0.111469] DMA: preallocated 128 KiB GFP_KERNEL pool for atomic allocations [ 0.111609] DMA: preallocated 128 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations [ 0.136666] cpu0: Ratio of byte access time to unaligned word access is 0.01, unaligned accesses are slow [ 0.137552] CCACHE: 4 banks, 16 ways, sets/bank=512, bytes/block=64 [ 0.137605] CCACHE: Index of the largest way enabled: 11 [ 0.157771] SCSI subsystem initialized [ 0.158766] usbcore: registered new interface driver usbfs [ 0.158875] usbcore: registered new interface driver hub [ 0.158975] usbcore: registered new device driver usb [ 0.159292] pps_core: LinuxPPS API ver. 1 registered [ 0.159329] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it> [ 0.159415] PTP clock support registered [ 0.159794] FPGA manager framework [ 0.161695] vgaarb: loaded [ 0.162052] clocksource: Switched to clocksource riscv_clocksource [ 0.182618] NET: Registered PF_INET protocol family [ 0.183621] IP idents hash table entries: 16384 (order: 5, 131072 bytes, linear) [ 0.188792] tcp_listen_portaddr_hash hash table entries: 512 (order: 1, 8192 bytes, linear) [ 0.188920] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear) [ 0.188980] TCP established hash table entries: 8192 (order: 4, 65536 bytes, linear) [ 0.189469] TCP bind hash table entries: 8192 (order: 6, 262144 bytes, linear) [ 0.191123] TCP: Hash tables configured (established 8192 bind 8192) [ 0.191905] UDP hash table entries: 512 (order: 2, 16384 bytes, linear) [ 0.192085] UDP-Lite hash table entries: 512 (order: 2, 16384 bytes, linear) [ 0.192549] NET: Registered PF_UNIX/PF_LOCAL protocol family [ 0.192680] PCI: CLS 0 bytes, default 64 [ 0.195059] workingset: timestamp_bits=62 max_order=18 bucket_order=0 [ 0.196385] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 249) [ 0.196451] io scheduler mq-deadline registered [ 0.196485] io scheduler kyber registered [ 0.196558] io scheduler bfq registered [ 0.198179] mpfs_irq_mux 20002000.syscon:interrupt-controller@54: mux configuration 0 [ 0.203505] irq: IRQ51: trimming hierarchy from :soc:interrupt-controller@c000000 [ 0.203653] irq: IRQ52: trimming hierarchy from :soc:interrupt-controller@c000000 [ 0.203784] irq: IRQ53: trimming hierarchy from :soc:interrupt-controller@c000000 [ 0.203941] irq: IRQ54: trimming hierarchy from :soc:interrupt-controller@c000000 [ 0.204083] irq: IRQ55: trimming hierarchy from :soc:interrupt-controller@c000000 [ 0.204208] irq: IRQ56: trimming hierarchy from :soc:interrupt-controller@c000000 [ 0.204334] irq: IRQ57: trimming hierarchy from :soc:interrupt-controller@c000000 [ 0.204470] irq: IRQ58: trimming hierarchy from :soc:interrupt-controller@c000000 [ 0.204598] irq: IRQ59: trimming hierarchy from :soc:interrupt-controller@c000000 [ 0.204739] irq: IRQ60: trimming hierarchy from :soc:interrupt-controller@c000000 [ 0.204866] irq: IRQ61: trimming hierarchy from :soc:interrupt-controller@c000000 [ 0.205021] irq: IRQ62: trimming hierarchy from :soc:interrupt-controller@c000000 [ 0.205148] irq: IRQ63: trimming hierarchy from :soc:interrupt-controller@c000000 [ 0.205273] irq: IRQ64: trimming hierarchy from :soc:interrupt-controller@c000000 [ 0.205420] irq: IRQ65: trimming hierarchy from :soc:interrupt-controller@c000000 [ 0.205548] irq: IRQ66: trimming hierarchy from :soc:interrupt-controller@c000000 [ 0.205682] irq: IRQ67: trimming hierarchy from :soc:interrupt-controller@c000000 [ 0.205809] irq: IRQ68: trimming hierarchy from :soc:interrupt-controller@c000000 [ 0.206102] irq: IRQ69: trimming hierarchy from :soc:interrupt-controller@c000000 [ 0.206245] irq: IRQ70: trimming hierarchy from :soc:interrupt-controller@c000000 [ 0.206370] irq: IRQ71: trimming hierarchy from :soc:interrupt-controller@c000000 [ 0.206509] irq: IRQ72: trimming hierarchy from :soc:interrupt-controller@c000000 [ 0.206636] irq: IRQ73: trimming hierarchy from :soc:interrupt-controller@c000000 [ 0.206761] irq: IRQ74: trimming hierarchy from :soc:interrupt-controller@c000000 [ 0.206902] irq: IRQ75: trimming hierarchy from :soc:interrupt-controller@c000000 [ 0.207042] irq: IRQ76: trimming hierarchy from :soc:interrupt-controller@c000000 [ 0.207171] irq: IRQ77: trimming hierarchy from :soc:interrupt-controller@c000000 [ 0.207297] irq: IRQ78: trimming hierarchy from :soc:interrupt-controller@c000000 [ 0.207443] irq: IRQ79: trimming hierarchy from :soc:interrupt-controller@c000000 [ 0.207571] irq: IRQ80: trimming hierarchy from :soc:interrupt-controller@c000000 [ 0.207707] irq: IRQ81: trimming hierarchy from :soc:interrupt-controller@c000000 [ 0.207832] irq: IRQ82: trimming hierarchy from :soc:interrupt-controller@c000000 [ 0.335683] Serial: 8250/16550 driver, 4 ports, IRQ sharing disabled [ 0.340903] 20100000.serial: ttyS0 at MMIO 0x20100000 (irq = 83, base_baud = 9375000) is a 16550A [ 0.343217] 20106000.serial: ttyS1 at MMIO 0x20106000 (irq = 84, base_baud = 9375000) is a 16550A [ 0.343322] printk: console [ttyS1] enabled [ 1.480744] loop: module loaded [ 1.485526] mpfs_dma_proxy mpfs-dma-proxy: proxy dma 4 channels initialized [ 1.647508] u-dma-buf udmabuf-ddr-c0: driver version = 4.5.3 [ 1.653327] u-dma-buf udmabuf-ddr-c0: major number = 244 [ 1.658882] u-dma-buf udmabuf-ddr-c0: minor number = 0 [ 1.664250] u-dma-buf udmabuf-ddr-c0: phys address = 0x0000000088000000 [ 1.671110] u-dma-buf udmabuf-ddr-c0: buffer size = 33554432 [ 1.677096] u-dma-buf udmabuf0: driver installed. [ 1.716082] u-dma-buf udmabuf-ddr-nc0: driver version = 4.5.3 [ 1.721906] u-dma-buf udmabuf-ddr-nc0: major number = 244 [ 1.727537] u-dma-buf udmabuf-ddr-nc0: minor number = 1 [ 1.732993] u-dma-buf udmabuf-ddr-nc0: phys address = 0x00000000c8000000 [ 1.739931] u-dma-buf udmabuf-ddr-nc0: buffer size = 33554432 [ 1.745989] u-dma-buf udmabuf1: driver installed. [ 1.767264] u-dma-buf udmabuf-ddr-nc-wcb0: driver version = 4.5.3 [ 1.773427] u-dma-buf udmabuf-ddr-nc-wcb0: major number = 244 [ 1.779410] u-dma-buf udmabuf-ddr-nc-wcb0: minor number = 2 [ 1.785222] u-dma-buf udmabuf-ddr-nc-wcb0: phys address = 0x00000000d8000000 [ 1.792511] u-dma-buf udmabuf-ddr-nc-wcb0: buffer size = 33554432 [ 1.798929] u-dma-buf udmabuf2: driver installed. [ 1.807627] microchip-corespi 20108000.spi: Registered SPI controller 0 [ 1.815503] microchip-corespi 20109000.spi: Registered SPI controller 1 [ 1.824666] CAN device driver interface [ 1.834280] macb 20110000.ethernet eth0: Cadence GEM rev 0x0107010c at 0x20110000 irq 87 (00:04:a3:6c:21:da) [ 1.846253] mss-dma-uio 60010000.dma-controller: registered device as dma-controller@60010000 [ 1.856868] mpfs_rtc 20124000.rtc: prescaler set to: 999999 [ 1.863445] mpfs_rtc 20124000.rtc: registered as rtc0 [ 1.868607] mpfs_rtc 20124000.rtc: setting system clock to 1970-01-01T00:00:00 UTC (0) [ 1.876757] i2c_dev: i2c /dev entries driver [ 1.882141] microchip-corei2c 2010a000.i2c: registered CoreI2C bus driver [ 1.889769] sdhci: Secure Digital Host Controller Interface driver [ 1.896026] sdhci: Copyright(c) Pierre Ossman [ 1.900485] sdhci-pltfm: SDHCI platform and OF driver helper [ 1.908423] usbcore: registered new interface driver usbhid [ 1.914144] usbhid: USB HID core driver [ 1.919027] mpfs-mailbox 37020800.mailbox: Registered MPFS mailbox controller driver [ 1.928339] NET: Registered PF_INET6 protocol family [ 1.936353] Segment Routing with IPv6 [ 1.940285] In-situ OAM (IOAM) with IPv6 [ 1.944444] sit: IPv6, IPv4 and MPLS over IPv4 tunneling driver [ 1.951728] NET: Registered PF_PACKET protocol family [ 1.956882] can: controller area network core [ 1.961498] NET: Registered PF_CAN protocol family [ 1.965547] mmc0: SDHCI controller on 20008000.mmc [20008000.mmc] using ADMA 64-bit [ 1.966342] can: raw protocol [ 1.977111] can: broadcast manager protocol [ 1.981377] can: netlink gateway - max_hops=1 [ 2.025869] random: crng init done [ 2.029441] mpfs-rng mpfs-rng: Registered MPFS hwrng [ 2.046325] mpfs-sys-controller syscontroller: Registered MPFS system controller [ 2.056087] clk: Disabling unused clocks [ 2.061450] Waiting for root device /dev/mmcblk0p3... [ 2.074105] mmc0: new high speed SDHC card at address aaaa [ 2.081906] mmcblk0: mmc0:aaaa SD32G 29.7 GiB [ 2.098836] mmcblk0: p1 p2 p3 [ 2.127014] EXT4-fs (mmcblk0p3): INFO: recovery required on readonly filesystem [ 2.134459] EXT4-fs (mmcblk0p3): write access will be enabled during recovery [ 2.187351] EXT4-fs (mmcblk0p3): recovery complete [ 2.196394] EXT4-fs (mmcblk0p3): mounted filesystem f35233e2-979f-4565-a9cb-11740d753440 ro with ordered data mode. Quota mode: disabled. [ 2.208952] VFS: Mounted root (ext4 filesystem) readonly on device 179:3. [ 2.216915] devtmpfs: mounted [ 2.230710] Freeing unused kernel image (initmem) memory: 2156K [ 2.236867] Run /sbin/init as init process [ 2.717341] systemd[1]: System time before build time, advancing clock. [ 2.738796] systemd[1]: Failed to find module 'autofs4' [ 2.794378] systemd[1]: systemd 254.4^ running in system mode (+PAM -AUDIT -SELINUX -APPARMOR +IMA -SMACK +SECCOMP -GCRYPT -GNUTLS +OPENSSL +ACL +BLKID -CURL -ELFUTILS -FIDO2 -IDN2 -IDN -IPTC +KMOD -LIBCRYPTSETUP +LIBFDISK -PCRE2 -PWQUALITY -P11KIT -QRENCODE -TPM2 -BZIP2 -LZ4 -XZ -ZLIB +ZSTD -BPF_FRAMEWORK +XKBCOMMON +UTMP +SYSVINIT default-hierarchy=hybrid) [ 2.826598] systemd[1]: Detected architecture riscv64. Welcome to OpenEmbedded nodistro.0! [ 2.862912] systemd[1]: Hostname set to <mpfs-disco-kit>. [ 3.996240] systemd[1]: Queued start job for default target Multi-User System. [ 4.039179] systemd[1]: Created slice Slice /system/getty. [ OK ] Created slice Slice /system/getty. [ 4.064428] systemd[1]: Created slice Slice /system/modprobe. [ OK ] Created slice Slice /system/modprobe. [ 4.088261] systemd[1]: Created slice Slice /system/serial-getty. [ OK ] Created slice Slice /system/serial-getty. [ 4.111480] systemd[1]: Created slice User and Session Slice. [ OK ] Created slice User and Session Slice. [ 4.134742] systemd[1]: Started Dispatch Password Requests to Console Directory Watch. [ OK ] Started Dispatch Password Requests to Console Directory Watch. [ 4.162670] systemd[1]: Started Forward Password Requests to Wall Directory Watch. [ OK ] Started Forward Password Requests to Wall Directory Watch. [ 4.186866] systemd[1]: Reached target Path Units. [ OK ] Reached target Path Units. [ 4.206383] systemd[1]: Reached target Remote File Systems. [ OK ] Reached target Remote File Systems. [ 4.230395] systemd[1]: Reached target Slice Units. [ OK ] Reached target Slice Units. [ 4.250441] systemd[1]: Reached target Swaps. [ OK ] Reached target Swaps. [ 4.325811] systemd[1]: Listening on RPCbind Server Activation Socket. [ OK ] Listening on RPCbind Server Activation Socket. [ 4.354543] systemd[1]: Reached target RPC Port Mapper. [ OK ] Reached target RPC Port Mapper. [ 4.379016] systemd[1]: Listening on initctl Compatibility Named Pipe. [ OK ] Listening on initctl Compatibility Named Pipe. [ 4.410075] systemd[1]: Journal Audit Socket was skipped because of an unmet condition check (ConditionSecurity=audit). [ 4.422449] systemd[1]: Listening on Journal Socket (/dev/log). [ OK ] Listening on Journal Socket (/dev/log). [ 4.447450] systemd[1]: Listening on Journal Socket. [ OK ] Listening on Journal Socket. [ 4.467752] systemd[1]: Listening on Network Service Netlink Socket. [ OK ] Listening on Network Service Netlink Socket. [ 4.491505] systemd[1]: Listening on udev Control Socket. [ OK ] Listening on udev Control Socket. [ 4.515078] systemd[1]: Listening on udev Kernel Socket. [ OK ] Listening on udev Kernel Socket. [ 4.539170] systemd[1]: Listening on User Database Manager Socket. [ OK ] Listening on User Database Manager Socket. [ 4.563175] systemd[1]: Huge Pages File System was skipped because of an unmet condition check (ConditionPathExists=/sys/kernel/mm/hugepages). [ 4.599035] systemd[1]: Mounting POSIX Message Queue File System... Mounting POSIX Message Queue File System... [ 4.628791] systemd[1]: Mounting Kernel Debug File System... Mounting Kernel Debug File System... [ 4.651182] systemd[1]: Kernel Trace File System was skipped because of an unmet condition check (ConditionPathExists=/sys/kernel/tracing). [ 4.665066] systemd[1]: Create List of Static Device Nodes was skipped because of an unmet condition check (ConditionFileNotEmpty=/lib/modules/6.6.51-linux4microchip+fpga-2024.09-g56d7964a57cd/modules.devname). [ 4.691603] systemd[1]: Starting Load Kernel Module configfs... Starting Load Kernel Module configfs... [ 4.721724] systemd[1]: Starting Load Kernel Module dm_mod... Starting Load Kernel Module dm_mod... [ 4.749886] systemd[1]: Starting Load Kernel Module drm... Starting Load Kernel Module drm... [ 4.777908] systemd[1]: Starting Load Kernel Module fuse... Starting Load Kernel Module fuse... [ 4.806083] systemd[1]: Starting Load Kernel Module loop... Starting Load Kernel Module loop... [ 4.834804] systemd[1]: Starting RPC Bind... Starting RPC Bind... [ 4.861712] systemd[1]: Starting File System Check on Root Device... Starting File System Check on Root Device... [ 4.900022] systemd[1]: Starting Journal Service... Starting Journal Service... [ 4.926679] systemd[1]: Load Kernel Modules was skipped because no trigger condition checks were met. [ 4.944675] systemd[1]: Starting Generate network units from Kernel command line... Starting Generate network units from Kernel command line... [ 4.962528] systemd[1]: Starting Apply Kernel Variables... Starting Apply Kernel Variables... [ 4.983693] systemd[1]: Starting Create Static Device Nodes in /dev gracefully... Starting Create Static Device Nodes in /dev gracefully... [ 5.004878] systemd[1]: Starting Coldplug All udev Devices... Starting Coldplug All udev Devices... [ 5.033754] systemd[1]: Started RPC Bind. [ OK ] Started 5.040247] systemd[1]: Mounted POSIX Message Queue File System. 1;39mRPC Bind. [ OK[ 5.049095] systemd[1]: Mounted Kernel Debug File System. ] Mounted POSIX Message Queue File System. [ OK ] Mounted Kernel Debu[ 5.065226] systemd[1]: modprobe@configfs.service: Deactivated successfully. g File System. [ 5.087925] systemd[1]: Finished Load Kernel Module configfs. [ OK ] Finished Load Kerne[ 5.105151] systemd[1]: modprobe@dm_mod.service: Deactivated successfully. l Module configfs. [ 5.115195] systemd-journald[104]: Collecting audit messages is disabled. [ 5.115443] systemd[1]: Finished Load Kernel Module dm_mod. [ OK ] Finished Load Kernel Module dm_mod. [ 5.150742] systemd[1]: modprobe@drm.service: Deactivated successfully. [ 5.158751] systemd[1]: Finished Load Kernel Module drm. [ OK ] Finished Load Kernel Module drm. [ 5.189908] systemd[1]: modprobe@fuse.service: Deactivated successfully. [ 5.198063] systemd[1]: Finished Load Kernel Module fuse. [ OK ] Finished Load Kernel Module fuse. [ 5.225413] systemd[1]: modprobe@loop.service: Deactivated successfully. [ 5.233629] systemd[1]: Finished Load Kernel Module loop. [ OK ] Finished Load Kernel Module loop. [ 5.260050] systemd[1]: Started Journal Service. [ OK ] Started Journal Service. [ OK ] Finished File System Check on Root Device. [ OK ] Finished Generate network units from Kernel command line. [ OK ] Finished Apply Kernel Variables. [ OK ] Finished Create Static Device Nodes in /dev gracefully. Mounting Kernel Configuration File System... Starting Remount Root and Kernel File Systems... Starting Repartition Root Disk... [ OK ] Mounted Kernel Configuration File System. [ 5.571553] EXT4-fs (mmcblk0p3): re-mounted f35233e2-979f-4565-a9cb-11740d753440 r/w. Quota mode: disabled. [ OK ] Finished Remount Root and Kernel File Systems. [ OK ] Finished Repartition Root Disk. Starting Grow Root File System... Starting Wait for udev To Complete Device Initialization... Starting User Database Manager... Starting Virtual Console Setup... [ OK ] Finished Wait for udev To Complete Device Initialization. [ OK ] Started Hardware RNG Entropy Gatherer Daemon. [ OK ] Finished Virtual Console Setup. [ OK ] Started User Database Manager.izing filesystem from 7772283 to 7772283 blocks [ OK ] Started Network Time Synchronization.n /dev... [ OK ] Reached target System Time Set.ceived client request to flush runtime journal. [ OK ] Started Network Name Resolution.tent Storage. [ OK ] Reached target Host and Network Name Lookups. [ 12.255058] platform 40000200.i2c: deferred probe pending [ 12.260615] platform 40000000.pwm: deferred probe pending [ OK ] Reached target System Initialization.e Events and Files... [ OK ] Started Daily Cleanup of Temporary Directories. [ OK ] Reached target Timer Units. [ OK ] Listening on Avahi mDNS/DNS-SD Stack Activation Socket. [ OK ] Listening on D-Bus System Message Bus Socket. Starting sshd.socket...e Files and Directories... [ OK ] Listening on sshd.socket.dom Seed. [ OK ] Reached target Socket Units.or Device Events and Files. [ OK ] Reached target Basic System.es and Directories. Starting Avahi mDNS/DNS-SD Stack... Starting D-Bus System Message Bus...n... [ OK ] Started A minimalistic network con…h DHCPv4, rdisc and DHCPv6 support. Starting IPv6 Packet Filtering Framework... Starting IPv4 Packet Filtering Framework... Starting User Login Management... Starting OpenSSH Key Generation... [ OK ] Finished IPv6 Packet Filtering Framework. [ OK ] Finished IPv4 Packet Filtering Framework. [ OK ] Started D-Bus System Message Bus. [ OK ] Finished OpenSSH Key Generation. [ OK ] Reached target Preparation for Network. Starting Network Configuration... [ OK ] Started Avahi mDNS/DNS-SD Stack. [ 13.022188] macb 20110000.ethernet end0: PHY [20110000.ethernet-ffffffff:0b] driver [Generic PHY] (irq=POLL) [ 13.032335] macb 20110000.ethernet end0: configuring for phy/sgmii link mode [ 13.041339] pps pps0: new PPS source ptp0 [ 13.054645] macb 20110000.ethernet: gem-ptp-timer ptp clock registered. [ OK ] Started User Login Management. [ OK ] Started Network Configuration. [ OK ] Reached target Network. Starting Permit User Sessions... [ OK ] Started Xinetd A Powerful Replacement For Inetd. [ OK ] Finished Permit User Sessions. [ OK ] Started Getty on tty1. [ OK ] Started Serial Getty on ttyS0. [ OK ] Started Serial Getty on ttyS1. [ OK ] Reached target Login Prompts. [ OK ] Reached target Multi-User System. Starting Record Runlevel Change in UTMP... [ OK ] Finished Record Runlevel Change in UTMP. OpenEmbedded nodistro.0 mpfs-disco-kit ttyS1 mpfs-disco-kit login: root This is version v2024.09 of the Polarfire SoC Yocto BSP. Updated images and documentation are available at: https://github.com/polarfire-soc/ root@mpfs-disco-kit:~#             本次分享就到这里。

回复了主题帖： 【microchip PolarFire SoC FPGA 套件】⑤尝试通过SoftConsole启动RISC-V内核

jobszheng5 发表于 2025-3-23 11:16 从去年就开始准备学习FPGA，结果到现在也没有成行。 唉 给自己定个小目标，一点点实现，加油，共勉

回复了主题帖： 【microchip PolarFire SoC FPGA 套件】简单uart的实现

这是纯硬件时序模拟实现串口通讯啊:loveliness:

发表了主题帖： 【microchip PolarFire SoC FPGA 套件】⑤尝试通过SoftConsole启动RISC-V内核

本帖最后由 cc1989summer 于 2025-3-22 22:29 编辑   https://bbs.eeworld.com.cn/thread-1308660-1-1.html   书接上回。我们知道PolarFire SoC FPGA是分为2大块的，一块是FPGA，通过Libero SoC编程驱动，一块是RISC-V SOC，通过SoftConsole编程驱动。 FPGA与RISC-V SOC相互独立，通过总线联通。因此想要通过SW1（隶属于FPGA  BANK0）驱动LED8（隶属于RISC-V SOC BANK2）还是有点困难的。 RISC-V SOC核的详细介绍，可参考：PolarFire_SoC_FPGA_MSS_Technical_Reference_Manual_VC     顺着藤摸下去，怎么驱动这个RISC-V SOC核呢？ 我咨询了microchip官方         这就不得不请蛋疼的Github出场，为啥说蛋疼呢，因为经常打不开。当然有时候可以打开。   https://github.com/polarfire-soc/polarfire-soc-discovery-kit-reference-design 这是我把该设计的附件下载下来了。       注意这个MPFS_DISCOVERY_KIT_REFERENCE_DESIGN.tcl，他是本文的关键。 这是该参考设计的架构图：     步骤一，在Libero中导入该参考设计。 Project——Execuie Script 需要注意一点：polarfire-soc-discovery-kit-reference-design-main文件夹需要尽量放置于靠近根目录的位置，比如 D:\Microchip\polarfire-soc-discovery-kit-reference-design-main 不可放置于桌面，文件路径过长会出错。             点击Run就可以了。 可以看到一个包括了RISC-V核在内的庞大体系。     Synthesize——constraints—— RUN PROGRAM Action后，就可以正常烧录了。 前面的步骤仅仅是对FPGA及SOC硬件线路进行了烧录。     要想驱动RISC-V SOC核，还需要使用Microchip的一大利器：SoftConsole   SoftConsole软件安装方法就不细说了。 安装好后，注意下载github (又是他) 裸机程序范例：polarfire-soc-bare-metal-examples         https://github.com/polarfire-soc/polarfire-soc-bare-metal-examples     官方只给出了下面3个例程。       1. 导入例程：         2：设置开发板型号           3.编译，下载调试：       4. 调试运行。   运行后，打开串口调试助手，共计3个串口，打开第2个。       每次按下SW2（SOC复位按钮）会出现如下画面：       随意发送一个字符，就开始系统自检测试。     依次进行 DDR Memory Test、SD Card Test、Ethernet(GEM) Test   具体程序细节还有待挖掘，先跑个代码试试是不！     本次分享就到这里。        

加入了学习《直播回放: Microchip - 为什么选择FPGA，而非MCU？》，观看 为什么选择FPGA，而非MCU？

回复了主题帖： 【microchip PolarFire SoC FPGA 套件】④求助：如何通过FPGA驱动SoC GPIO？

卿小小 发表于 2025-3-10 16:41 帖子内容质量很棒，对于您的问题做如下解答： 1.对于流水灯的功能来讲，驱动逻辑侧的7个LED已经够了； ... 谢谢您的细致指点，我再好好研究下，，第一次用microchip FPGA，尤其是包含SOC的FPGA，很多方面还不熟悉，网上资料也很少，这次争取搞明白了。:congratulate:

发表了主题帖： 【microchip PolarFire SoC FPGA 套件】④求助：如何通过FPGA驱动SoC GPIO？

https://bbs.eeworld.com.cn/thread-1307977-1-1.html 书接上回，通过Verilog语言运行了一个跑马灯的程序，遗憾的是8个LED只成功驱动了其中7个， 前面7个都属于FPGA直属的BANK0；而LED8挂载在Bank2（也就是属于SoC的GPIO）     通过常规的方式根本没有选不了BANK2 E1端口。     查阅官方说明文档，原来用到SOC的IO，需要通过PolarFireSoC MSS Configurator软件来设置。             如果想实现一个最简单的功能，通过按钮SW1控制LED8的亮灭。       SW1：BANK0 T19，直属于FPGA HSIO LED8：BANK2 E1（复用GPIO_1_9），直属于SOC（MSS） GPIO      查阅了官方资料：       PolarFireSoC MSS Configurator 设置如下：                       然后在Libero SoC v2024.2中导入刚才的MSS 设置，         最右边的逻辑块就是设置好的SOC。 其左侧有2个RESET GPIO_RESET_N_F2M：SOC GPIO的复位？ MSS_RESET_N_F2M：SOC的复位？                 编译、设置管脚（GPIO_RESET_N_F2M设置为SW1 BANK0 T19,MSS_RESET_N_F2M_0设置为SW2 BANK0 U18），但烧录后仍无法控制GPIO_1_9 (LED8)亮灭。     困于以上问题，究竟如何通过FPGA驱动SoC GPIO呢？      

发表了主题帖： 【microchip PolarFire SoC FPGA 套件】③艰难啃下基于verilog语言的跑马灯

https://bbs.eeworld.com.cn/thread-1307592-1-1.html   书接上回，上次跑了一个基于官方的范例，也就是个最简单的 与门 电路。 也就是这样的：按下按键1或按键2，LED1灯亮。基本学习了如何编写程序及如何烧录。        有了初步的入门，那么怎么进一步编写自己的程序呢，看到开发板上8个LED陷入沉思，何不写个跑马灯的程序呢。   多方查资料学习，于是就有了如下的程序。   其中OSC_RC2MHZ_0是 Libero自带的时钟程序块（Macro Libray中）。     需要说明，把选中到OSC_RC2MHZ_0选中到电路图中，需要把左端脚上拉（Tie High）     cc03_0是我自编的基于verilog语言的程序，也是本文的重点。 首先新建一个 Creat HDL，选择verilog。       要实现跑马灯就需要比较精准的时钟，我们使用了2MHz的时钟源，每1个周期是（1/2,000,000 S ）要想实现1秒钟计时，就需要数数到2,000,000 LED的跑马灯效果就是通过移位来实现,RST是复位功能。 比如 00000001 向左移位1位 00000010 再向左移位1位 00000100 再向左移位1位 00001000 再向左移位1位 00010000 再向左移位1位 00100000 再向左移位1位 01000000 再向左移位1位 10000000 等到最高位是1时就恢复到最初状态 00000001            程序如下： module cc03( clk,rst_n,led); input clk; input rst_n; output reg [6:0] led; reg [20:0] counter; //计数器 always@(posedge clk) if(!rst_n)//低电平复位 counter <= 0; else if(counter == 21'd1999999) //1秒 counter <= 0; else counter <= counter + 1'b1; always@(posedge clk) if(!rst_n) led <= 7'b0000001; else if(counter == 21'd1999998)begin if(led == 7'b1000000) led <= 7'b0000001; else led <= led << 1; end else led <= led; endmodule     眼睑的你可能看到了，我这里LED【6：0】怎么只有7个LED，待会会提。   verilog程序编写完，点击Check HDL File。如果程序有错会提示：         程序检查无误就点击 Build Hierarchy。       将刚才编写好的cc03.v程序拖到电路图中。 置顶对应引脚（rst_n，LED 6：0）   Synthesize通过后，设置好对应引脚。                 发现LED8对应的E1引脚无法选择，可能因为其是MSS（RISC-V核） I/O BANK的缘故，目前还没学会使用RISC-V核的IO，暂时就不用这个LED了。   最后编译下载程序就可以实现跑马灯效果了。         [localvideo]e113055628df4bc770aac3a940d70384[/localvideo]   本次分享就到这里。  

回复了主题帖： 【microchip PolarFire SoC FPGA 套件】②并不算一帆风顺的点灯之旅

ccccccc@ 发表于 2025-2-27 14:38 这个板子还是很强大的，不过阅读英语比较吃力的话，可以试试ai（不过ai也会有些问题存在，比如乱回复，回答 ... 加油，攻克这个复杂板子