In dual mode, two ADCs are used: an ADC master and an ADC slave. The beginning of
conversion is triggered by the ADC master to the ADC slave. The converted data of both
master and slave can be read in parallel by reading the multi-mode data register ADC_CDR.
The status bits can be also read in parallel by reading the multi-mode status register
ADC_CSR.
The STM32F30x ADC family presents several dual modes, each of which is explained
independently in this document:
• Injected simultaneous mode: the master and slave injected channel groups are
converted simultaneously after receiving an external trigger.
• Regular simultaneous mode: the master and slave regular channels are converted
simultaneously.
• Interleaved mode: the master ADC starts immediately; then, after a programmed
delay, the slave ADC starts.
• Alternate trigger mode: when the first trigger occurs, all injected master ADC
channels in the group are converted; when the second trigger occurs, all injected slave
ADC channels in the group are converted