module last(
input clk,
input clk_c,
input wire set,
output reg en,
output reg[3:0] cnt,
input wire rst,
input wire in_a,
input wire in_b,
input wire in_c,
output reg q_a,
output reg q_b,
output reg q_c,
output reg rset,
output reg rset_1
//output reg sec
);
always @(posedge clk_c)
begin:clk_com
if(set)
en=1;
//sec