OPT 2
INCLUDE kxarm.h
INCLUDE option.inc
INCLUDE s2440addr.inc
INCLUDE memcfg.inc
OPT 1
OPT 128
; Pre-defined constants.
;
USERMODE EQU 0x10
FIQMODE EQU 0x11
IRQMODE EQU 0x12
SVCMODE EQU 0x13
ABORTMODE EQU 0x17
UNDEFMODE EQU 0x1b
MODEMASK EQU 0x1f
NOINT EQU 0xc0
; Stack locations.
;
SVCStack EQU (_STACK_BASEADDRESS-0x2800) ; 0x33ff5800 ~
UserStack EQU (_STACK_BASEADDRESS-0x3800) ; 0x33ff4800 ~
UndefStack EQU (_STACK_BASEADDRESS-0x2400) ; 0x33ff5c00 ~
AbortStack EQU (_STACK_BASEADDRESS-0x2000) ; 0x33ff6000 ~
IRQStack EQU (_STACK_BASEADDRESS-0x1000) ; 0x33ff7000 ~
FIQStack EQU (_STACK_BASEADDRESS-0x0) ; 0x33ff8000 ~
;------------------------------------------------------------------------------
; Sleep state constants
;
; Location of sleep data
; BUGBUG - this needs to be declared as a local var.
SLEEPDATA_BASE_PHYSICAL EQU 0x30028000
WORD_SIZE EQU 0x4
; Sleep State memory locations
SleepState_Data_Start EQU (0)
SleepState_WakeAddr EQU (SleepState_Data_Start + 0)
SleepState_MMUCTL EQU (SleepState_WakeAddr + WORD_SIZE)
SleepState_MMUTTB EQU (SleepState_MMUCTL + WORD_SIZE)
SleepState_MMUDOMAIN EQU (SleepState_MMUTTB + WORD_SIZE)
SleepState_SVC_SP EQU (SleepState_MMUDOMAIN + WORD_SIZE)
SleepState_SVC_SPSR EQU (SleepState_SVC_SP + WORD_SIZE)
SleepState_FIQ_SPSR EQU (SleepState_SVC_SPSR + WORD_SIZE)
SleepState_FIQ_R8 EQU (SleepState_FIQ_SPSR + WORD_SIZE)
SleepState_FIQ_R9 EQU (SleepState_FIQ_R8 + WORD_SIZE)
SleepState_FIQ_R10 EQU (SleepState_FIQ_R9 + WORD_SIZE)
SleepState_FIQ_R11 EQU (SleepState_FIQ_R10 + WORD_SIZE)
SleepState_FIQ_R12 EQU (SleepState_FIQ_R11 + WORD_SIZE)
SleepState_FIQ_SP EQU (SleepState_FIQ_R12 + WORD_SIZE)
SleepState_FIQ_LR EQU (SleepState_FIQ_SP + WORD_SIZE)
SleepState_ABT_SPSR EQU (SleepState_FIQ_LR + WORD_SIZE)
SleepState_ABT_SP EQU (SleepState_ABT_SPSR + WORD_SIZE)
SleepState_ABT_LR EQU (SleepState_ABT_SP + WORD_SIZE)
SleepState_IRQ_SPSR EQU (SleepState_ABT_LR + WORD_SIZE)
SleepState_IRQ_SP EQU (SleepState_IRQ_SPSR + WORD_SIZE)
SleepState_IRQ_LR EQU (SleepState_IRQ_SP + WORD_SIZE)
SleepState_UND_SPSR EQU (SleepState_IRQ_LR + WORD_SIZE)
SleepState_UND_SP EQU (SleepState_UND_SPSR + WORD_SIZE)
SleepState_UND_LR EQU (SleepState_UND_SP + WORD_SIZE)
SleepState_SYS_SP EQU (SleepState_UND_LR + WORD_SIZE)
SleepState_SYS_LR EQU (SleepState_SYS_SP + WORD_SIZE)
SleepState_Data_End EQU (SleepState_SYS_LR + WORD_SIZE)
SLEEPDATA_SIZE EQU (SleepState_Data_End - SleepState_Data_Start) / 4
IMPORT main ; C entrypoint for Steppingstone loader.
EXPORT MMU_EnableICache
EXPORT MMU_SetAsyncBusMode
STARTUPTEXT
LEAF_ENTRY StartUp
b ResetHandler
b .
b .
b .
b .
b .
b .
b .
PowerOffCPU
str r1, [r0] ; Enable SDRAM self-refresh
str r3, [r2] ; MISCCR Setting
str r5, [r4] ; Power Off !!
b .
; Resume handler code.
;
WAKEUP_POWER_OFF
; Release SCLKn after wake-up from the POWER_OFF mode.
ldr r1, =MISCCR
ldr r0, [r1]
bic r0, r0, #(7SCLK, SCKE:L->H.
str r0, [r1]
; Set up the memory control registers.
;
add r0, pc, #SMRDATA - (. + 8)
ldr r1, =BWSCON ; BWSCON Address.
add r2, r0, #52 ; End address of SMRDATA.
3
ldr r3, [r0], #4
str r3, [r1], #4
cmp r2, r0
bne %B3
mov r0, #0x2000
4
subs r0, r0, #1
bne %B4
;------------------------------------------------------------------------------
; Recover Process : Starting Point
;
; 1. Checksum Calculation saved Data
ldr r5, =SLEEPDATA_BASE_PHYSICAL ; pointer to physical address of reserved Sleep mode info data structure
mov r3, r5 ; pointer for checksum calculation
ldr r2, =0x0
ldr r0, =(SLEEPDATA_SIZE-1) ; get size of data structure to do checksum on
50
ldr r1, [r3], #4 ; pointer to SLEEPDATA
and r1, r1, #0x1
mov r1, r1, ROR #31
add r2, r2, r1
subs r0, r0, #1 ; dec the count
bne %b50 ; loop till done
ldr r0,=GSTATUS3
ldr r3, [r0] ; get the Sleep data checksum from the Power Manager Scratch pad register
cmp r2, r3 ; compare to what we saved before going to sleep
bne BringUpWinCE ; bad news - do a cold boot
; 2. MMU Enable
ldr r10, [r5, #SleepState_MMUDOMAIN] ; load the MMU domain access info
ldr r9, [r5, #SleepState_MMUTTB] ; load the MMU TTB info
ldr r8, [r5, #SleepState_MMUCTL] ; load the MMU control info
ldr r7, [r5, #SleepState_WakeAddr ] ; load the LR address
nop
nop
nop
nop
nop
; if software reset
mov r1, #0
teq r1, r7
bne %f60
b BringUpWinCE
; wakeup routine
60 mcr p15, 0, r10, c3, c0, 0 ; setup access to domain 0
mcr p15, 0, r9, c2, c0, 0 ; PT address
mcr p15, 0, r0, c8, c7, 0 ; flush I+D TLBs
mcr p15, 0, r8, c1, c0, 0 ; restore MMU control
; 3. Jump to Kernel Image's fw.s (Awake_address)
mov pc, r7 ; jump to new VA (back up Power management stack)
nop
BringUpWinCE
; bad news, data lose, bring up wince again
mov r0, #2
ldr r1, =GSTATUS2
str r0, [r1]
LTORG
;-----------------------------------
; Steppingstone loader entry point.
;-----------------------------------
ResetHandler
ldr r0, =WTCON ; disable the watchdog timer.
ldr r1, =0x0
str r1, [r0]
ldr r0, =INTMSK ; mask all first-level interrupts.
ldr r1, =0xffffffff
str r1, [r0]
ldr r0, =INTSUBMSK ; mask all second-level interrupts.
ldr r1, =0x7fff
str r1, [r0]
; CLKDIVN
ldr r0,=CLKDIVN
ldr r1,=0x5
;ldr r1,=0x7 ; 0x0 = 1:1:1 , 0x1 = 1:1:2 , 0x2 = 1:2:2 , 0x3 = 1:2:4, 0x4 = 1:4:4, 0x5 = 1:4:8, 0x6 = 1:3:3, 0x7 = 1:3:6
str r1,[r0]
; BATT_FLT
ldr r1, =MISCCR
ldr r0, [r1]
bic r0, r0, #(7
stm32/stm8