哇哇哇，这个才是我的：
void i2c1_evt_isr()
{
switch (I2C_GetLastEvent(I2C1))
{
/************************** Master Invoke**************************************/
case I2C_EVENT_MASTER_MODE_SELECT: /* EV5 */
// MSL SB BUSY 30001
if(!check_begin)
i2c_comm_state = COMM_IN_PROCESS;
if (Direction == Receiver)
{
if (DeviceOffset != 0xffffffff)
I2C_Send7bitAddress(I2C1, SlaveADDR, I2C_Direction_Transmitter);
else
/* Send slave Address for read */
I2C_Send7bitAddress(I2C1, SlaveADDR, I2C_Direction_Receiver);
}
else
{
/* Send slave Address for write */
I2C_Send7bitAddress(I2C1, SlaveADDR, I2C_Direction_Transmitter);
}
I2C_ITConfig(I2C1, I2C_IT_BUF , ENABLE);//also TxE int allowed
break;
/********************** Master Receiver events ********************************/
case I2C_EVENT_MASTER_RECEIVER_MODE_SELECTED: /* EV6 */
// MSL BUSY ADDR 0x30002
if (RxLength == 1)
{
/* Disable I2C1 acknowledgement */
I2C_AcknowledgeConfig(I2C1, DISABLE);
/* Send I2C1 STOP Condition */
I2C_GenerateSTOP(I2C1, ENABLE);
}
break;
case I2C_EVENT_MASTER_BYTE_RECEIVED: /* EV7 */
// MSL BUSY RXNE 0x30040
/* Store I2C1 received data */
*pRxBuffer1++ = I2C_ReceiveData (I2C1);
RxLength--;
/* Disable ACK and send I2C1 STOP condition before receiving the last data */
if (RxLength == 1)
{
/* Disable I2C1 acknowledgement */
I2C_AcknowledgeConfig(I2C1, DISABLE);
/* Send I2C1 STOP Condition */
I2C_GenerateSTOP(I2C1, ENABLE);
}
if (RxLength == 0)
{
MasterReceptionComplete = 1;
i2c_comm_state = COMM_DONE;
PV_flag_1 = 0;
}
break;
/************************* Master Transmitter events **************************/
case I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED: /* EV8 just after EV6 */
//BUSY, MSL, ADDR, TXE and TRA 0x70082
if (check_begin)
{
check_begin = FALSE;
WriteComplete = 1;
i2c_comm_state = COMM_DONE;
I2C_ITConfig(I2C1, I2C_IT_EVT | I2C_IT_BUF |I2C_IT_ERR, DISABLE);
I2C_GenerateSTOP(I2C1, ENABLE);
PV_flag_1 = 0;
break;
}
if (DeviceOffset != 0xffffffff)
I2C_SendData(I2C1, DeviceOffset);
else
{
I2C_SendData(I2C1, *pTxBuffer1++);
TxLength--;
}
break;
case I2C_EVENT_MASTER_BYTE_TRANSMITTING: /* EV8 */
//TRA, BUSY, MSL, TXE 0x70080
if (Direction == Receiver)
{
DeviceOffset = 0xffffffff; // enter read-phase 2 (the same as no memory space)
I2C_ITConfig(I2C1, I2C_IT_BUF , DISABLE);
while ((I2C1->CR1 & 0x200) == 0x200);
I2C_GenerateSTART(I2C1, ENABLE);
break;
}
if (TxLength >0)
{
I2C_SendData(I2C1, *pTxBuffer1++);
TxLength--;
}
/* Disable the I2C_IT_BUF interrupt after sending the last buffer data
(last EV8) to no allow a new interrupt with TxE and only BTF could generate it */
else if(TxLength == 0)
{
I2C_ITConfig(I2C1, I2C_IT_BUF, DISABLE);
I2C_GenerateSTOP(I2C1, ENABLE); }
break;
case I2C_EVENT_MASTER_BYTE_TRANSMITTED: /* EV8-2 */
//TRA, BUSY, MSL, TXE and BTF 0x70084
if (Direction == Transmitter)
{
MasterTransitionComplete = 1;
I2C_ITConfig(I2C1, I2C_IT_EVT | I2C_IT_BUF, DISABLE);
// enable AF and SB and ADDR interrupt
I2C_ITConfig(I2C1, I2C_IT_EVT | I2C_IT_ERR, ENABLE);
check_begin = TRUE;
i2c_comm_state = CHECK_IN_PROCESS;
//while ((I2C1->CR1 & 0x200) == 0x200);
if(I2C1->CR1 & 0x200)
I2C1->CR1 &= 0xFDFF;
I2C_GenerateSTART(I2C1, ENABLE);
break;
} else
{
break;
}
/********************** Slave Transmitter Events ******************************/
case I2C_EVENT_SLAVE_TRANSMITTER_ADDRESS_MATCHED: /* EV1 */
//TRA, BUSY, TXE and ADDR 0x60082
i2c_comm_state = COMM_IN_PROCESS;
I2C_SendData(I2C1, *pTxBuffer1++);
TxLength--;
I2C_ITConfig(I2C1, I2C_IT_BUF , ENABLE); // also allow TxE
break;
case I2C_EVENT_SLAVE_BYTE_TRANSMITTED: /* EV3 */
//TRA, BUSY, TXE and BTF 0x60084
if (TxLength>0)
{
I2C_SendData(I2C1, *pTxBuffer1++);
TxLength--;
}
break;
case 0x60080:
// TRA, BUSY,TXE, no BTF
// if this case added, above case would never be reached
if (TxLength>0)
{
I2C_SendData(I2C1, *pTxBuffer1++);
TxLength--;
if (TxLength ==0)
{
SlaveTransitionComplete =1;
i2c_comm_state = COMM_DONE;
I2C_ITConfig(I2C1, I2C_IT_BUF , DISABLE);//close TxE int
I2C_ITConfig(I2C1, I2C_IT_ERR , ENABLE);//to handle AF from master receiver
PV_flag_1 = 0;
}
}
break;
/************************ Slave Receiver Events *******************************/
case I2C_EVENT_SLAVE_RECEIVER_ADDRESS_MATCHED: /* EV1 */
// BUSY ADDR 0x20002
i2c_comm_state = COMM_IN_PROCESS;
I2C_ITConfig(I2C1, I2C_IT_BUF , ENABLE); // also allow RxNE
break;
case I2C_EVENT_SLAVE_BYTE_RECEIVED: /* EV2 */
// BUSY RxNE 0x20040
*pRxBuffer1++ = I2C_ReceiveData(I2C1);
RxLength--; // controled by i2c1 sender
if (RxLength == 0)
{
SlaveReceptionComplete = 1;
I2C_ITConfig(I2C1, I2C_IT_BUF , DISABLE); // only EVT(STOPF) int
I2C_ITConfig(I2C1, I2C_IT_EVT , ENABLE);
}
break;
case I2C_EVENT_SLAVE_STOP_DETECTED: /* EV4 */
// STOPF 0x10
/* Clear I2C2 STOPF flag: read of I2C_SR1 followed by a write in I2C_CR1 */
(void)(I2C_GetITStatus(I2C1, I2C_IT_STOPF));
I2C_Cmd(I2C1, ENABLE);
i2c_comm_state = COMM_DONE;
PV_flag_1 = 0;
//I2C_ITConfig(I2C2, I2C_IT_EVT, DISABLE);
break;
case 0x20050:
// used when Rx and Tx handley by one mcu at the same time
// receive last data and clear stopf
*pRxBuffer1++ = I2C_ReceiveData(I2C1);
RxLength--;
SlaveReceptionComplete = 1;
(void)(I2C_GetITStatus(I2C1, I2C_IT_STOPF));
I2C_Cmd(I2C1, ENABLE);
I2C_ITConfig(I2C1, I2C_IT_EVT | I2C_IT_BUF, DISABLE);
I2C_ITConfig(I2C1, I2C_IT_BUF , DISABLE);
break;
case 0x20010:
// busy+stopf
// when last data read isr exist, there would be stopf flag
//which is set during read ISR. and as sender's check begin
// busy also set
i2c_comm_state = CHECK_IN_PROCESS;
(void)(I2C_GetITStatus(I2C1, I2C_IT_STOPF));
I2C_Cmd(I2C1, ENABLE);
break;
/******************************* default Events *******************************/
default:
break;
}
}
void i2c1_err_isr()
{
if (I2C_GetFlagStatus(I2C1, I2C_FLAG_AF))
{
if (check_begin)
I2C_GenerateSTART(I2C1, ENABLE);
else if (I2C1->SR2 &0x01)
{
I2C_GenerateSTOP(I2C1, ENABLE);
i2c_comm_state = COMM_EXIT;
PV_flag_1 = 0;
}
I2C_ClearFlag(I2C1, I2C_FLAG_AF);
}
if (I2C_GetFlagStatus(I2C1, I2C_FLAG_BERR))
{
if (I2C1->SR2 &0x01)
{
I2C_GenerateSTOP(I2C1, ENABLE);
i2c_comm_state = COMM_EXIT;
PV_flag_1 = 0;
}
I2C_ClearFlag(I2C1, I2C_FLAG_BERR);
}
}
stm32/stm8