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1. FPGA 读写DDR3出现有规律的错误？（有没有大牛画过DDR3的板子，重金求画板） 11/3107 PCB设计 2014-01-20
  
  置顶，求大牛帮忙分析解决，谢谢
2. Spartan6 FPGA MIG驱动DDR3出现错误？ 3/5937 FPGA/CPLD 2014-01-20
  
  再次置顶，再求大牛帮忙分析，谢谢了
3. FPGA 读写DDR3出现有规律的错误？（有没有大牛画过DDR3的板子，重金求画板） 11/3107 PCB设计 2014-01-20
  
  chenzhufly 发表于 2014-1-14 10:41 哈哈这个可以有多重啊我可以滴
  您有邮箱吗？我们可以联系一下。
4. FPGA 读写DDR3出现有规律的错误？（有没有大牛画过DDR3的板子，重金求画板） 11/3107 PCB设计 2014-01-20
  
  kz_zank 发表于 2014-1-14 10:05 遇到过类似的问题是FPGA代码有问题，基本可以排除PCB的问题。因为我不是写代码的，我不知道具体是错在哪里 ...
  这个代码在开发板上是正常跑的，但是在我们自己的板子上就不行，所以我到认为不应该是代码的问题，但是就像您说的2.5V又是可以的，所以这个问题就很复杂。不知道您有没有邮箱，方便的话，我可以把全部资料发给您帮忙看看。
5. FPGA 读写DDR3出现有规律的错误？（有没有大牛画过DDR3的板子，重金求画板） 11/3107 PCB设计 2014-01-12
  
  没有办法啊，同事画过两次都失败了，没有办法，只能求助外面了。
6. Spartan6 FPGA MIG驱动DDR3出现错误？ 3/5937 FPGA/CPLD 2014-01-12
  
  改过一次，用过offset in before什么的？也不知道改的对不对，反正就试了好几种，一点反应都没有，大侠能帮忙改一下约束吗？谢谢！一下是开发板的： # Spartan-6 SP605 Evaluation Platform Net fpga_0_RS232_Uart_1_RX_pin LOC = G22 | IOSTANDARD=LVCMOS33; Net fpga_0_RS232_Uart_1_TX_pin LOC = F21 | IOSTANDARD=LVCMOS33; Net fpga_0_LEDs_4Bit_GPIO_IO_pin LOC = D1 | IOSTANDARD=LVCMOS15; Net fpga_0_LEDs_4Bit_GPIO_IO_pin LOC = F3 | IOSTANDARD=LVCMOS15; Net fpga_0_LEDs_4Bit_GPIO_IO_pin LOC = E4 | IOSTANDARD=LVCMOS15; Net fpga_0_LEDs_4Bit_GPIO_IO_pin LOC = H6 | IOSTANDARD=LVCMOS15; Net fpga_0_MCB_DDR3_mcbx_dram_addr_pin IOSTANDARD = SSTL15_II; Net fpga_0_MCB_DDR3_mcbx_dram_addr_pin IOSTANDARD = SSTL15_II; Net fpga_0_MCB_DDR3_mcbx_dram_addr_pin IOSTANDARD = SSTL15_II; Net fpga_0_MCB_DDR3_mcbx_dram_addr_pin IOSTANDARD = SSTL15_II; Net fpga_0_MCB_DDR3_mcbx_dram_addr_pin IOSTANDARD = SSTL15_II; Net fpga_0_MCB_DDR3_mcbx_dram_addr_pin IOSTANDARD = SSTL15_II; Net fpga_0_MCB_DDR3_mcbx_dram_addr_pin IOSTANDARD = SSTL15_II; Net fpga_0_MCB_DDR3_mcbx_dram_addr_pin IOSTANDARD = SSTL15_II; Net fpga_0_MCB_DDR3_mcbx_dram_addr_pin IOSTANDARD = SSTL15_II; Net fpga_0_MCB_DDR3_mcbx_dram_addr_pin IOSTANDARD = SSTL15_II; Net fpga_0_MCB_DDR3_mcbx_dram_addr_pin IOSTANDARD = SSTL15_II; Net fpga_0_MCB_DDR3_mcbx_dram_addr_pin IOSTANDARD = SSTL15_II; Net fpga_0_MCB_DDR3_mcbx_dram_addr_pin IOSTANDARD = SSTL15_II; Net fpga_0_MCB_DDR3_mcbx_dram_ba_pin IOSTANDARD = SSTL15_II; Net fpga_0_MCB_DDR3_mcbx_dram_ba_pin IOSTANDARD = SSTL15_II; Net fpga_0_MCB_DDR3_mcbx_dram_ba_pin IOSTANDARD = SSTL15_II; Net fpga_0_MCB_DDR3_mcbx_dram_ras_n_pin IOSTANDARD = SSTL15_II; Net fpga_0_MCB_DDR3_mcbx_dram_cas_n_pin IOSTANDARD = SSTL15_II; Net fpga_0_MCB_DDR3_mcbx_dram_we_n_pin IOSTANDARD = SSTL15_II; Net fpga_0_MCB_DDR3_mcbx_dram_cke_pin IOSTANDARD = SSTL15_II; Net fpga_0_MCB_DDR3_mcbx_dram_clk_pin IOSTANDARD = DIFF_SSTL15_II; Net fpga_0_MCB_DDR3_mcbx_dram_clk_n_pin IOSTANDARD = DIFF_SSTL15_II; Net fpga_0_MCB_DDR3_mcbx_dram_dq_pin IOSTANDARD = SSTL15_II; Net fpga_0_MCB_DDR3_mcbx_dram_dq_pin IOSTANDARD = SSTL15_II; Net fpga_0_MCB_DDR3_mcbx_dram_dq_pin IOSTANDARD = SSTL15_II; Net fpga_0_MCB_DDR3_mcbx_dram_dq_pin IOSTANDARD = SSTL15_II; Net fpga_0_MCB_DDR3_mcbx_dram_dq_pin IOSTANDARD = SSTL15_II; Net fpga_0_MCB_DDR3_mcbx_dram_dq_pin IOSTANDARD = SSTL15_II; Net fpga_0_MCB_DDR3_mcbx_dram_dq_pin IOSTANDARD = SSTL15_II; Net fpga_0_MCB_DDR3_mcbx_dram_dq_pin IOSTANDARD = SSTL15_II; Net fpga_0_MCB_DDR3_mcbx_dram_dq_pin IOSTANDARD = SSTL15_II; Net fpga_0_MCB_DDR3_mcbx_dram_dq_pin IOSTANDARD = SSTL15_II; Net fpga_0_MCB_DDR3_mcbx_dram_dq_pin IOSTANDARD = SSTL15_II; Net fpga_0_MCB_DDR3_mcbx_dram_dq_pin IOSTANDARD = SSTL15_II; Net fpga_0_MCB_DDR3_mcbx_dram_dq_pin IOSTANDARD = SSTL15_II; Net fpga_0_MCB_DDR3_mcbx_dram_dq_pin IOSTANDARD = SSTL15_II; Net fpga_0_MCB_DDR3_mcbx_dram_dq_pin IOSTANDARD = SSTL15_II; Net fpga_0_MCB_DDR3_mcbx_dram_dq_pin IOSTANDARD = SSTL15_II; Net fpga_0_MCB_DDR3_mcbx_dram_dqs_pin IOSTANDARD = DIFF_SSTL15_II; Net fpga_0_MCB_DDR3_mcbx_dram_dqs_n_pin IOSTANDARD = DIFF_SSTL15_II; Net fpga_0_MCB_DDR3_mcbx_dram_udqs_pin IOSTANDARD = DIFF_SSTL15_II; Net fpga_0_MCB_DDR3_mcbx_dram_udqs_n_pin IOSTANDARD = DIFF_SSTL15_II; Net fpga_0_MCB_DDR3_mcbx_dram_udm_pin IOSTANDARD = SSTL15_II; Net fpga_0_MCB_DDR3_mcbx_dram_ldm_pin IOSTANDARD = SSTL15_II; Net fpga_0_MCB_DDR3_mcbx_dram_odt_pin IOSTANDARD = SSTL15_II; Net fpga_0_MCB_DDR3_mcbx_dram_ddr3_rst_pin IOSTANDARD = SSTL15_II; Net fpga_0_MCB_DDR3_rzq_pin IOSTANDARD = SSTL15_II; Net fpga_0_MCB_DDR3_zio_pin IOSTANDARD = SSTL15_II; Net fpga_0_clk_1_sys_clk_p_pin TNM_NET = sys_clk_pin; TIMESPEC TS_sys_clk_pin = PERIOD sys_clk_pin 200000 kHz; Net fpga_0_clk_1_sys_clk_p_pin LOC = L20 | IOSTANDARD=LVDS_33 | DIFF_TERM = TRUE; Net fpga_0_clk_1_sys_clk_n_pin LOC = L22 | IOSTANDARD=LVDS_33 | DIFF_TERM = TRUE; Net fpga_0_rst_1_sys_rst_pin TIG; Net fpga_0_rst_1_sys_rst_pin LOC = H4 | IOSTANDARD=LVCMOS15 | PULLUP | TIG;
7. 有没有人搞过can的ip核，网上的资源可以用吗？ 7/8400 FPGA/CPLD 2012-08-05
  
  我以前也想搞一搞，但是我们是做工程的，需要的是可靠性，咨询了Xilinx的技术支持以及S2C公司的技术支持，他们有专门的IP核，不过价格比较贵的，网上的我下了几个，也还是不敢用，怕出什么问题。上次参加了个培训，咨询了老师，老实说像做CAN总线这样的，FPGA本身并不是优势，除非IP核免费开放，如果非要用就可以外挂SJA1000，稳定可靠。我现在做CAN HUB就是这么做的。
8. 【免费租用】Xilinx Spartan-6 FPGA 嵌入式套件！（12月26日更新） 43/16802 FPGA/CPLD 2012-08-05
  
  MARK
9. FPGA应用设计资料整合帖（不断补充中） 274/71421 FPGA/CPLD 2012-08-05
  
  MARK一下

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