不足论 发表于 2017-5-26 08:55 轮流设置top去编译

大神  我轮流去仿真的时候问题就出在这段程序上   但是看不懂  求帮看看 architecture STRUCTURE of hdmi_in_proc_sys_reset_0_0 is   attribute C_AUX_RESET_HIGH : string;   attribute C_AUX_RESET_HIGH of U0 : label is "1'b0";   attribute C_AUX_RST_WIDTH : integer;   attribute C_AUX_RST_WIDTH of U0 : label is 4;   attribute C_EXT_RESET_HIGH : string;   attribute C_EXT_RESET_HIGH of U0 : label is "1'b0";   attribute C_EXT_RST_WIDTH : integer;   attribute C_EXT_RST_WIDTH of U0 : label is 4;   attribute C_FAMILY : string;   attribute C_FAMILY of U0 : label is "zynq";   attribute C_NUM_BUS_RST : integer;   attribute C_NUM_BUS_RST of U0 : label is 1;   attribute C_NUM_INTERCONNECT_ARESETN : integer;   attribute C_NUM_INTERCONNECT_ARESETN of U0 : label is 1;   attribute C_NUM_PERP_ARESETN : integer;   attribute C_NUM_PERP_ARESETN of U0 : label is 1;   attribute C_NUM_PERP_RST : integer;   attribute C_NUM_PERP_RST of U0 : label is 1; begin U0: entity work.hdmi_in_proc_sys_reset_0_0_proc_sys_reset      port map (       aux_reset_in => aux_reset_in,       bus_struct_reset(0) => bus_struct_reset(0),       dcm_locked => dcm_locked,       ext_reset_in => ext_reset_in,       interconnect_aresetn(0) => interconnect_aresetn(0),       mb_debug_sys_rst => mb_debug_sys_rst,       mb_reset => mb_reset,       peripheral_aresetn(0) => peripheral_aresetn(0),       peripheral_reset(0) => peripheral_reset(0),       slowest_sync_clk => slowest_sync_clk     ); end STRUCTURE; 错误提示： 'compile' step failed with error(s). Please check the Tcl console output or 'E:/HDMItest/T1/t1/t1.sim/sim_1/behav/xvhdl.log' file for more information.

不足论 发表于 2017-5-23 11:04 轮流编译，定位问题原因

请问是轮流一个模块一个模块的仿真吗？  请问具体怎么去做呢？小白求解

整个工程来自这里   https://github.com/Digilent/Zybo-hdmi-in 太大没有办法上传   求大神给看看

源程序如下 --Copyright 1986-2016 Xilinx, Inc. All Rights Reserved. ---------------------------------------------------------------------------------- --Tool Version: Vivado v.2016.4 (win64) Build 1756540 Mon Jan 23 19:11:23 MST 2017 --Date        : Mon May 22 19:28:27 2017 --Host        : DESKTOP-QFQQKAV running 64-bit major release  (build 9200) --Command     : generate_target hdmi_in_wrapper.bd --Design      : hdmi_in_wrapper --Purpose     : IP block netlist ---------------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity hdmi_in_wrapper is   port (     DDR_addr : inout STD_LOGIC_VECTOR ( 14 downto 0 );     DDR_ba : inout STD_LOGIC_VECTOR ( 2 downto 0 );     DDR_cas_n : inout STD_LOGIC;     DDR_ck_n : inout STD_LOGIC;     DDR_ck_p : inout STD_LOGIC;     DDR_cke : inout STD_LOGIC;     DDR_cs_n : inout STD_LOGIC;     DDR_dm : inout STD_LOGIC_VECTOR ( 3 downto 0 );     DDR_dq : inout STD_LOGIC_VECTOR ( 31 downto 0 );     DDR_dqs_n : inout STD_LOGIC_VECTOR ( 3 downto 0 );     DDR_dqs_p : inout STD_LOGIC_VECTOR ( 3 downto 0 );     DDR_odt : inout STD_LOGIC;     DDR_ras_n : inout STD_LOGIC;     DDR_reset_n : inout STD_LOGIC;     DDR_we_n : inout STD_LOGIC;     FIXED_IO_ddr_vrn : inout STD_LOGIC;     FIXED_IO_ddr_vrp : inout STD_LOGIC;     FIXED_IO_mio : inout STD_LOGIC_VECTOR ( 53 downto 0 );     FIXED_IO_ps_clk : inout STD_LOGIC;     FIXED_IO_ps_porb : inout STD_LOGIC;     FIXED_IO_ps_srstb : inout STD_LOGIC;     HDMI_OEN : out STD_LOGIC_VECTOR ( 0 to 0 );     TMDS_clk_n : in STD_LOGIC;     TMDS_clk_p : in STD_LOGIC;     TMDS_data_n : in STD_LOGIC_VECTOR ( 2 downto 0 );     TMDS_data_p : in STD_LOGIC_VECTOR ( 2 downto 0 );     btns_4bits_tri_i : in STD_LOGIC_VECTOR ( 3 downto 0 );     ddc_scl_io : inout STD_LOGIC;     ddc_sda_io : inout STD_LOGIC;     hdmi_hpd_tri_o : out STD_LOGIC_VECTOR ( 0 to 0 );     iic_0_scl_io : inout STD_LOGIC;     iic_0_sda_io : inout STD_LOGIC;     leds_4bits_tri_io : inout STD_LOGIC_VECTOR ( 3 downto 0 );     sws_4bits_tri_i : in STD_LOGIC_VECTOR ( 3 downto 0 );     vga_b : out STD_LOGIC_VECTOR ( 4 downto 0 );     vga_g : out STD_LOGIC_VECTOR ( 5 downto 0 );     vga_hs : out STD_LOGIC;     vga_r : out STD_LOGIC_VECTOR ( 4 downto 0 );     vga_vs : out STD_LOGIC   ); end hdmi_in_wrapper; architecture STRUCTURE of hdmi_in_wrapper is   component hdmi_in is   port (     DDC_scl_i : in STD_LOGIC;     DDC_scl_o : out STD_LOGIC;     DDC_scl_t : out STD_LOGIC;     DDC_sda_i : in STD_LOGIC;     DDC_sda_o : out STD_LOGIC;     DDC_sda_t : out STD_LOGIC;     DDR_cas_n : inout STD_LOGIC;     DDR_cke : inout STD_LOGIC;     DDR_ck_n : inout STD_LOGIC;     DDR_ck_p : inout STD_LOGIC;     DDR_cs_n : inout STD_LOGIC;     DDR_reset_n : inout STD_LOGIC;     DDR_odt : inout STD_LOGIC;     DDR_ras_n : inout STD_LOGIC;     DDR_we_n : inout STD_LOGIC;     DDR_ba : inout STD_LOGIC_VECTOR ( 2 downto 0 );     DDR_addr : inout STD_LOGIC_VECTOR ( 14 downto 0 );     DDR_dm : inout STD_LOGIC_VECTOR ( 3 downto 0 );     DDR_dq : inout STD_LOGIC_VECTOR ( 31 downto 0 );     DDR_dqs_n : inout STD_LOGIC_VECTOR ( 3 downto 0 );     DDR_dqs_p : inout STD_LOGIC_VECTOR ( 3 downto 0 );     FIXED_IO_mio : inout STD_LOGIC_VECTOR ( 53 downto 0 );     FIXED_IO_ddr_vrn : inout STD_LOGIC;     FIXED_IO_ddr_vrp : inout STD_LOGIC;     FIXED_IO_ps_srstb : inout STD_LOGIC;     FIXED_IO_ps_clk : inout STD_LOGIC;     FIXED_IO_ps_porb : inout STD_LOGIC;     IIC_0_sda_i : in STD_LOGIC;     IIC_0_sda_o : out STD_LOGIC;     IIC_0_sda_t : out STD_LOGIC;     IIC_0_scl_i : in STD_LOGIC;     IIC_0_scl_o : out STD_LOGIC;     IIC_0_scl_t : out STD_LOGIC;     TMDS_clk_p : in STD_LOGIC;     TMDS_clk_n : in STD_LOGIC;     TMDS_data_p : in STD_LOGIC_VECTOR ( 2 downto 0 );     TMDS_data_n : in STD_LOGIC_VECTOR ( 2 downto 0 );     btns_4bits_tri_i : in STD_LOGIC_VECTOR ( 3 downto 0 );     hdmi_hpd_tri_o : out STD_LOGIC_VECTOR ( 0 to 0 );     leds_4bits_tri_i : in STD_LOGIC_VECTOR ( 3 downto 0 );     leds_4bits_tri_o : out STD_LOGIC_VECTOR ( 3 downto 0 );     leds_4bits_tri_t : out STD_LOGIC_VECTOR ( 3 downto 0 );     sws_4bits_tri_i : in STD_LOGIC_VECTOR ( 3 downto 0 );     vga_b : out STD_LOGIC_VECTOR ( 4 downto 0 );     vga_g : out STD_LOGIC_VECTOR ( 5 downto 0 );     vga_hs : out STD_LOGIC;     vga_r : out STD_LOGIC_VECTOR ( 4 downto 0 );     vga_vs : out STD_LOGIC;     HDMI_OEN : out STD_LOGIC_VECTOR ( 0 to 0 )   );   end component hdmi_in;   component IOBUF is   port (     I : in STD_LOGIC;     O : out STD_LOGIC;     T : in STD_LOGIC;     IO : inout STD_LOGIC   );   end component IOBUF;   signal ddc_scl_i : STD_LOGIC;   signal ddc_scl_o : STD_LOGIC;   signal ddc_scl_t : STD_LOGIC;   signal ddc_sda_i : STD_LOGIC;   signal ddc_sda_o : STD_LOGIC;   signal ddc_sda_t : STD_LOGIC;   signal iic_0_scl_i : STD_LOGIC;   signal iic_0_scl_o : STD_LOGIC;   signal iic_0_scl_t : STD_LOGIC;   signal iic_0_sda_i : STD_LOGIC;   signal iic_0_sda_o : STD_LOGIC;   signal iic_0_sda_t : STD_LOGIC;   signal leds_4bits_tri_i_0 : STD_LOGIC_VECTOR ( 0 to 0 );   signal leds_4bits_tri_i_1 : STD_LOGIC_VECTOR ( 1 to 1 );   signal leds_4bits_tri_i_2 : STD_LOGIC_VECTOR ( 2 to 2 );   signal leds_4bits_tri_i_3 : STD_LOGIC_VECTOR ( 3 to 3 );   signal leds_4bits_tri_io_0 : STD_LOGIC_VECTOR ( 0 to 0 );   signal leds_4bits_tri_io_1 : STD_LOGIC_VECTOR ( 1 to 1 );   signal leds_4bits_tri_io_2 : STD_LOGIC_VECTOR ( 2 to 2 );   signal leds_4bits_tri_io_3 : STD_LOGIC_VECTOR ( 3 to 3 );   signal leds_4bits_tri_o_0 : STD_LOGIC_VECTOR ( 0 to 0 );   signal leds_4bits_tri_o_1 : STD_LOGIC_VECTOR ( 1 to 1 );   signal leds_4bits_tri_o_2 : STD_LOGIC_VECTOR ( 2 to 2 );   signal leds_4bits_tri_o_3 : STD_LOGIC_VECTOR ( 3 to 3 );   signal leds_4bits_tri_t_0 : STD_LOGIC_VECTOR ( 0 to 0 );   signal leds_4bits_tri_t_1 : STD_LOGIC_VECTOR ( 1 to 1 );   signal leds_4bits_tri_t_2 : STD_LOGIC_VECTOR ( 2 to 2 );   signal leds_4bits_tri_t_3 : STD_LOGIC_VECTOR ( 3 to 3 ); begin ddc_scl_iobuf: component IOBUF      port map (       I => ddc_scl_o,       IO => ddc_scl_io,       O => ddc_scl_i,       T => ddc_scl_t     ); ddc_sda_iobuf: component IOBUF      port map (       I => ddc_sda_o,       IO => ddc_sda_io,       O => ddc_sda_i,       T => ddc_sda_t     ); hdmi_in_i: component hdmi_in      port map (       DDC_scl_i => ddc_scl_i,       DDC_scl_o => ddc_scl_o,       DDC_scl_t => ddc_scl_t,       DDC_sda_i => ddc_sda_i,       DDC_sda_o => ddc_sda_o,       DDC_sda_t => ddc_sda_t,       DDR_addr(14 downto 0) => DDR_addr(14 downto 0),       DDR_ba(2 downto 0) => DDR_ba(2 downto 0),       DDR_cas_n => DDR_cas_n,       DDR_ck_n => DDR_ck_n,       DDR_ck_p => DDR_ck_p,       DDR_cke => DDR_cke,       DDR_cs_n => DDR_cs_n,       DDR_dm(3 downto 0) => DDR_dm(3 downto 0),       DDR_dq(31 downto 0) => DDR_dq(31 downto 0),       DDR_dqs_n(3 downto 0) => DDR_dqs_n(3 downto 0),       DDR_dqs_p(3 downto 0) => DDR_dqs_p(3 downto 0),       DDR_odt => DDR_odt,       DDR_ras_n => DDR_ras_n,       DDR_reset_n => DDR_reset_n,       DDR_we_n => DDR_we_n,       FIXED_IO_ddr_vrn => FIXED_IO_ddr_vrn,       FIXED_IO_ddr_vrp => FIXED_IO_ddr_vrp,       FIXED_IO_mio(53 downto 0) => FIXED_IO_mio(53 downto 0),       FIXED_IO_ps_clk => FIXED_IO_ps_clk,       FIXED_IO_ps_porb => FIXED_IO_ps_porb,       FIXED_IO_ps_srstb => FIXED_IO_ps_srstb,       HDMI_OEN(0) => HDMI_OEN(0),       IIC_0_scl_i => iic_0_scl_i,       IIC_0_scl_o => iic_0_scl_o,       IIC_0_scl_t => iic_0_scl_t,       IIC_0_sda_i => iic_0_sda_i,       IIC_0_sda_o => iic_0_sda_o,       IIC_0_sda_t => iic_0_sda_t,       TMDS_clk_n => TMDS_clk_n,       TMDS_clk_p => TMDS_clk_p,       TMDS_data_n(2 downto 0) => TMDS_data_n(2 downto 0),       TMDS_data_p(2 downto 0) => TMDS_data_p(2 downto 0),       btns_4bits_tri_i(3 downto 0) => btns_4bits_tri_i(3 downto 0),       hdmi_hpd_tri_o(0) => hdmi_hpd_tri_o(0),       leds_4bits_tri_i(3) => leds_4bits_tri_i_3(3),       leds_4bits_tri_i(2) => leds_4bits_tri_i_2(2),       leds_4bits_tri_i(1) => leds_4bits_tri_i_1(1),       leds_4bits_tri_i(0) => leds_4bits_tri_i_0(0),       leds_4bits_tri_o(3) => leds_4bits_tri_o_3(3),       leds_4bits_tri_o(2) => leds_4bits_tri_o_2(2),       leds_4bits_tri_o(1) => leds_4bits_tri_o_1(1),       leds_4bits_tri_o(0) => leds_4bits_tri_o_0(0),       leds_4bits_tri_t(3) => leds_4bits_tri_t_3(3),       leds_4bits_tri_t(2) => leds_4bits_tri_t_2(2),       leds_4bits_tri_t(1) => leds_4bits_tri_t_1(1),       leds_4bits_tri_t(0) => leds_4bits_tri_t_0(0),       sws_4bits_tri_i(3 downto 0) => sws_4bits_tri_i(3 downto 0),       vga_b(4 downto 0) => vga_b(4 downto 0),       vga_g(5 downto 0) => vga_g(5 downto 0),       vga_hs => vga_hs,       vga_r(4 downto 0) => vga_r(4 downto 0),       vga_vs => vga_vs     ); iic_0_scl_iobuf: component IOBUF      port map (       I => iic_0_scl_o,       IO => iic_0_scl_io,       O => iic_0_scl_i,       T => iic_0_scl_t     ); iic_0_sda_iobuf: component IOBUF      port map (       I => iic_0_sda_o,       IO => iic_0_sda_io,       O => iic_0_sda_i,       T => iic_0_sda_t     ); leds_4bits_tri_iobuf_0: component IOBUF      port map (       I => leds_4bits_tri_o_0(0),       IO => leds_4bits_tri_io(0),       O => leds_4bits_tri_i_0(0),       T => leds_4bits_tri_t_0(0)     ); leds_4bits_tri_iobuf_1: component IOBUF      port map (       I => leds_4bits_tri_o_1(1),       IO => leds_4bits_tri_io(1),       O => leds_4bits_tri_i_1(1),       T => leds_4bits_tri_t_1(1)     ); leds_4bits_tri_iobuf_2: component IOBUF      port map (       I => leds_4bits_tri_o_2(2),       IO => leds_4bits_tri_io(2),       O => leds_4bits_tri_i_2(2),       T => leds_4bits_tri_t_2(2)     ); leds_4bits_tri_iobuf_3: component IOBUF      port map (       I => leds_4bits_tri_o_3(3),       IO => leds_4bits_tri_io(3),       O => leds_4bits_tri_i_3(3),       T => leds_4bits_tri_t_3(3)     ); end STRUCTURE; 是一个HDMI转VGA的程序，源程序本身没有检查出错误，但是仿真和综合过不去。求大神帮我看看

nixixu 发表于 2017-5-23 09:55 代码看不懂

这个是他的执行日志  我以为上传这个就能看懂