2.8 来看下

先谢过，下了

library ieee; use ieee.std_logic_1164.all; entity fredevider5 is port (        clkin: in std_logic;         clkout: out std_logic ); end; architecture behavior of fredevider5 is signal counter:integer range 0 to 4; signal temp1,temp2:std_logic; begin         process(clkin)         begin         if rising_edge(clkin) then                 if counter=4 then                         counter