HRESULT WINAPI ConnMgrQueryDetailedStatus(   CONNMGR_CONNECTION_DETAILED_STATUS *pStatusBuffer,   DWORD *pcbBufferSize ); dwType==CM_CONNTYPE_CELLULAR 时的dwSubtype 可能的值为： CM_CONNSUBTYPE_CELLULAR_UNKNOWN The connection subtype is unknown. CM_CONNSUBTYPE_CELLULAR_CSD A CSD cellular connection. This type is treated as a dial-up connection. The CSD subtype is the default connection subtype for cellular connections. CM_CONNSUBTYPE_CELLULAR_GPRS A GPRS cellular connection. CM_CONNSUBTYPE_CELLULAR_1XRTT A 1xRTT cellular connection. CM_CONNSUBTYPE_CELLULAR_1XEVDO A 1xEVDO cellular connection. This connection subtype is treated the same as the CM_CONNSUBTYPE_CELLULAR_1XRTT subtype. CM_CONNSUBTYPE_CELLULAR_1XEVDV A 1xEVDV cellular connection. This connection subtype is treated the same as the CM_CONNSUBTYPE_CELLULAR_1XRTT subtype. CM_CONNSUBTYPE_CELLULAR_EDGE An EDGE cellular connection. This connection subtype is treated the same as the CM_CONNSUBTYPE_CELLULAR_GPRS subtype. CM_CONNSUBTYPE_CELLULAR_UMTS A UMTS cellular connection. This connection subtype is treated the same as the CM_CONNSUBTYPE_CELLULAR_GPRS subtype. CM_CONNSUBTYPE_CELLULAR_VOICE A voice cellular connection. CM_CONNSUBTYPE_CELLULAR_PTT A Push-To-Talk cellular connection. This is currently not supported. CM_CONNSUBTYPE_CELLULAR_HSDPA A High Speed Downlink Packet Access connection.

uip移植初步成功，已经可以实现ARP/PING/UDP， PING成功图片

delay.h,delay,c    延时函数 buffer.h,buffer,c    缓冲管理函数 uart128.h,uart128.c  双串口接口函数 global.h        全局变量定义 rtl8019.h,rtl8019.c 网络接口函数 helleworld.c   主程序

整合UIP中的RTL8019.H/C作了一个完整测试的程序！程序输出如下： 11:55:05> now uart1 ! 11:55:05> delay 1s! 11:55:06> now uart0! 11:55:06>   11:55:06>  RAMTEST START ! 11:55:06> -----POINTER  READ AND WRITE EXTERNAL 32K RAM---------- 11:55:07> 0 READ AND WRITE NO WAIT  PC7 RELEASED ! 11:55:07> init system ok! 11:55:07> now test system-ram  all is 32k ! 11:55:07> ----now write  ram  0000 11:55:08> ----write ok 11:55:08> ----now check write 11:55:08> ---- test system-ram  end! 11:55:08> ----now write  ram  0055 11:55:08> ----write ok 11:55:09> ----now check write 11:55:09> ---- test system-ram  end! 11:55:09> ----now write  ram  00aa 11:55:09> ----write ok 11:55:09> ----now check write 11:55:10> ---- test system-ram  end! 11:55:10> ----now write  ram  0000 11:55:10> ----write ok 11:55:10> ----now check write 11:55:11> ---- test system-ram  end! 11:55:11> 1 READ AND WRITE 1 WAIT  PC7 RELEASED ! 11:55:11> init system ok! 11:55:11> now test system-ram  all is 32k ! 11:55:12> ----now write  ram  0000 11:55:12> ----write ok 11:55:12> ----now check write 11:55:12> ---- test system-ram  end! 11:55:12> ----now write  ram  0055 11:55:12> ----write ok 11:55:13> ----now check write 11:55:13> ---- test system-ram  end! 11:55:13> ----now write  ram  00aa 11:55:13> ----write ok 11:55:14> ----now check write 11:55:14> ---- test system-ram  end! 11:55:14> ----now write  ram  0000 11:55:14> ----write ok 11:55:15> ----now check write 11:55:15> ---- test system-ram  end! 11:55:15> 2 READ AND WRITE 2 WAIT  PC7 RELEASED ! 11:55:15> init system ok! 11:55:16> now test system-ram  all is 32k ! 11:55:16> ----now write  ram  0000 11:55:16> ----write ok 11:55:17> ----now check write 11:55:17> ---- test system-ram  end! 11:55:17> ----now write  ram  0055 11:55:17> ----write ok 11:55:17> ----now check write 11:55:18> ---- test system-ram  end! 11:55:18> ----now write  ram  00aa 11:55:18> ----write ok 11:55:18> ----now check write 11:55:19> ---- test system-ram  end! 11:55:19> ----now write  ram  0000 11:55:19> ----write ok 11:55:20> ----now check write 11:55:20> ---- test system-ram  end! 11:55:20> 3 READ AND WRITE 2+1 WAIT  PC7 RELEASED ! 11:55:20> init system ok! 11:55:21> now test system-ram  all is 32k ! 11:55:21> ----now write  ram  0000 11:55:21> ----write ok 11:55:21> ----now check write 11:55:22> ---- test system-ram  end! 11:55:22> ----now write  ram  0055 11:55:22> ----write ok 11:55:22> ----now check write 11:55:23> ---- test system-ram  end! 11:55:23> ----now write  ram  00aa 11:55:23> ----write ok 11:55:24> ----now check write 11:55:24> ---- test system-ram  end! 11:55:24> ----now write  ram  0000 11:55:24> ----write ok 11:55:25> ----now check write 11:55:25> ---- test system-ram  end! 11:55:25> ******POINTER  READ AND WRITE EXTERNAL 32K RAM******* 11:55:26>   11:55:26> -----BUFFER READ AND WRITE EXTERNAL 32K RAM---------- 11:55:27> 4  READ AND WRITE  NOWAIT PC7  NO RELEASED ! 11:55:27> init system ok! 11:55:27> now test system-ram  all is 32k ! 11:55:28> ----now write  ram  0000 11:55:28> ----write ok 11:55:28> ----now check write 11:55:28> ---- test system-ram  end! 11:55:28> ----now write  ram  0055 11:55:29> ----write ok 11:55:29> ----now check write 11:55:29> ---- test system-ram  end! 11:55:29> ----now write  ram  00aa 11:55:30> ----write ok 11:55:30> ----now check write 11:55:30> ---- test system-ram  end! 11:55:30> ----now write  ram  0000 11:55:31> ----write ok 11:55:31> ----now check write 11:55:31> ---- test system-ram  end! 11:55:31> 5  READ AND WRITE  1 WAIT PC7  NO RELEASED ! 11:55:32> init system ok! 11:55:32> now test system-ram  all is 32k ! 11:55:32> ----now write  ram  0000 11:55:32> ----write ok 11:55:33> ----now check write 11:55:33> ---- test system-ram  end! 11:55:33> ----now write  ram  0055 11:55:33> ----write ok 11:55:34> ----now check write 11:55:34> ---- test system-ram  end! 11:55:34> ----now write  ram  00aa 11:55:34> ----write ok 11:55:34> ----now check write 11:55:35> ---- test system-ram  end! 11:55:35> ----now write  ram  0000 11:55:35> ----write ok 11:55:35> ----now check write 11:55:36> ---- test system-ram  end! 11:55:36> 6  READ AND WRITE  2WAIT PC7  NO RELEASED ! 11:55:36> init system ok! 11:55:37> now test system-ram  all is 32k ! 11:55:37> ----now write  ram  0000 11:55:37> ----write ok 11:55:37> ----now check write 11:55:38> ---- test system-ram  end! 11:55:38> ----now write  ram  0055 11:55:38> ----write ok 11:55:38> ----now check write 11:55:39> ---- test system-ram  end! 11:55:39> ----now write  ram  00aa 11:55:39> ----write ok 11:55:39> ----now check write 11:55:40> ---- test system-ram  end! 11:55:40> ----now write  ram  0000 11:55:40> ----write ok 11:55:40> ----now check write 11:55:41> ---- test system-ram  end! 11:55:41> 7  READ AND WRITE  2+1WAIT PC7  NO RELEASED ! 11:55:41> init system ok! 11:55:42> now test system-ram  all is 32k ! 11:55:42> ----now write  ram  0000 11:55:42> ----write ok 11:55:42> ----now check write 11:55:43> ---- test system-ram  end! 11:55:43> ----now write  ram  0055 11:55:43> ----write ok 11:55:43> ----now check write 11:55:43> ---- test system-ram  end! 11:55:44> ----now write  ram  00aa 11:55:44> ----write ok 11:55:44> ----now check write 11:55:44> ---- test system-ram  end! 11:55:45> ----now write  ram  0000 11:55:45> ----write ok 11:55:45> ----now check write 11:55:45> ---- test system-ram  end! 11:55:45>   11:55:46> *******BUFFER READ AND WRITE EXTERNAL 32K RAM*********** 11:55:46> ---- RAM TEST OK!----- 11:55:46>   11:55:47>  now test rtl8019as! 11:55:47> now show first rtl8019as reg ! 11:55:47>   11:55:47>  Realtek 8019AS Register dump 11:55:48>  REG  Page0 Page1 Page2 Page3 11:55:48> 0000    0021    0061    00a1    00e1    11:55:48> 0001    0000    0008    000a    0034    11:55:49> 0002    00ff    002a    0000    0000    11:55:49> 0003    00c3    00a0    00ff    0008    11:55:50> 0004    0003    0040    0032    0080    11:55:50> 0005    0000    00b6    00ff    0000    11:55:50> 0006    0000    0084    00ff    0000    11:55:51> 0007    0080    00df    00ff    00ff    11:55:51> 0008    00ff    0010    00ff    0000    11:55:51> 0009    000f    0059    00ff    00fe    11:55:52> 000a    0050    0042    00ff    00ff    11:55:52> 000b    0070    0000    00ff    00fe    11:55:52> 000c    0016    0010    00c4    00ff    11:55:53> 000d    0000    004d    00e0    00fe    11:55:53> 000e    0000    0000    0084    00ff    11:55:54> 000f    0000    0001    0080    00ff    11:55:54> now init rtl8019as! 11:55:54> now show second rtl8019as reg ! 11:55:54>   11:55:55>  Realtek 8019AS Register dump 11:55:55>  REG  Page0 Page1 Page2 Page3 11:55:55> 0000    0023    0063    00a3    00e3    11:55:56> 0001    0000    006d    0046    0030    11:55:56> 0002    00ff    0069    0060    0000    11:55:57> 0003    0046    0072    00ff    000c    11:55:57> 0004    0003    0072    0040    0080    11:55:57> 0005    0000    006f    00ff    0020    11:55:58> 0006    0000    006b    00ff    0000    11:55:58> 0007    0080    0046    00ff    00ff    11:55:59> 0008    00ff    0010    00ff    0000    11:55:59> 0009    000f    0059    00ff    00fe    11:55:59> 000a    0050    0042    00ff    00ff    11:56:00> 000b    0070    0000    00ff    00fe    11:56:00> 000c    0016    0010    00c4    00ff    11:56:01> 000d    0000    004d    00e0    00fe    11:56:01> 000e    0000    0000    00d8    00ff    11:56:02> 000f    0000    0001    0091    00ff    11:56:02> ----test rtl8019as end! 完整的输出如上. 现在可以移植UIP了! ^-^  哈哈!!!!!

测试UIP中的 RTL8019.H/.C，检测是否需要参数修改！！ 首先建立一个项目，来调用UIP的RTL8019.H/.C  

[url=http://www.ouravr.com/bbs/bbs_upload88916/files_6/armok01126905.jpg][/url] 红色的代表RTL8019的ID0 和ID1 只有RTL8019AS有的,属于特征代码,读到0X50/0X70代表RTL8019AS复位正常,可以工作!! 绿色部分: 0x6d,0x69,0x72,0x72,0x6f,0x72是我设置的网卡的MAC地址 是字符! //本机MAC和IP设置 static char MYMAC[6] = { 'm','i','r','r','o','r' }; 至此UART0/1,外部RAM读写,和网络接口都已经完成,下面开始移植UIP0.9!!!

看到上述的PAGE3有问题 和PAGE2 的数值一样！！ 修改代码得到如下串口输出结果！！

下面初始化RTL8019AS后再读取寄存器中的值，，以验证写入的正确性！这样就可以正常读写RTL8019AS！！！ 1.先调用SHOWREG读取RTL8019AS的寄存器数值； 2.init_net()来初始化RTL8019AS 3.调用SHOWREG读取RTL8019AS的寄存器数值； 4.如果正确，则对RTL8019AS的读写就OK了！！！

下面主要测试外部RAM和RTL8019的读写！！！ 1.外部RAM的测试已经完成 ATEMGA128-16读写外部32KRAM-70NS的完整测试程序!!   http://www2.ouravr.com/bbs/bbs_c ... ge_no=1&bbs_id=1031 2.RTL8019AS读写成功！！！

12:38:29> init system ok! 12:38:29> now test system-ram  all is 32k ! 12:38:29> ----now write  ram  0000 12:38:29> ----write ok 12:38:29> ----now check write 12:38:29> addr = 1100 =0000 12:38:29> addr = 1101 =006c 12:38:29> addr = 1102 =0082 12:38:29> addr = 1103 =0094 12:38:29> addr = 1104 =006a 12:38:29> addr = 1105 =0080 12:38:29> addr = 1106 =00f0 12:38:29> addr = 1107 =0048 12:38:29> addr = 1108 =0087 12:38:29> addr = 1109 =00c2 12:38:29> addr = 110a =0044 12:38:29> addr = 110b =004a 12:38:29> addr = 110c =0013 12:38:29> addr = 110d =00b0 12:38:29> addr = 110e =0080 12:38:29> addr = 110f =00c3 12:38:29> ---- test system-ram  end! 12:38:29> ----now write  ram  0055 12:38:29> ----write ok 12:38:29> ----now check write 12:38:30> addr = 1100 =0055 12:38:30> addr = 1101 =006c 12:38:30> addr = 1102 =0082 12:38:30> addr = 1103 =0094 12:38:30> addr = 1104 =006a 12:38:30> addr = 1105 =0080 12:38:30> addr = 1106 =00f0 12:38:30> addr = 1107 =0048 12:38:30> addr = 1108 =0087 12:38:30> addr = 1109 =00c2 12:38:30> addr = 110a =0044 12:38:30> addr = 110b =004a 12:38:30> addr = 110c =0013 12:38:30> addr = 110d =00b0 12:38:30> addr = 110e =0080 12:38:30> addr = 110f =00c3 12:38:30> ---- test system-ram  end! 12:38:30> ----now write  ram  00aa 12:38:30> ----write ok 12:38:30> ----now check write 12:38:30> addr = 1100 =00aa 12:38:30> addr = 1101 =006c 12:38:30> addr = 1102 =0082 12:38:30> addr = 1103 =0094 12:38:30> addr = 1104 =006a 12:38:30> addr = 1105 =0080 12:38:30> addr = 1106 =00f0 12:38:30> addr = 1107 =0048 12:38:30> addr = 1108 =0087 12:38:30> addr = 1109 =00c2 12:38:30> addr = 110a =0044 12:38:30> addr = 110b =004a 12:38:30> addr = 110c =0013 12:38:30> addr = 110d =00b0 12:38:30> addr = 110e =0080 12:38:30> addr = 110f =00c3 12:38:30> ---- test system-ram  end! 12:38:30> ----now write  ram  0000 12:38:30> ----write ok 12:38:30> ----now check write 12:38:30> addr = 1100 =0000 12:38:30> addr = 1101 =006c 12:38:30> addr = 1102 =0082 12:38:30> addr = 1103 =0094 12:38:30> addr = 1104 =006a 12:38:30> addr = 1105 =0080 12:38:30> addr = 1106 =00f0 12:38:30> addr = 1107 =0048 12:38:30> addr = 1108 =0087 12:38:30> addr = 1109 =00c2 12:38:30> addr = 110a =0044 12:38:31> addr = 110b =004a 12:38:31> addr = 110c =0013 12:38:31> addr = 110d =00b0 12:38:31> addr = 110e =0080 12:38:31> addr = 110f =00c3 12:38:31> ---- test system-ram  end!

} */ //测试RTL8019AS void test_net(void) { } // void main(void) { unsigned int k=0; unsigned int i=0,j=0; unsigned char DATA,u;   //COM=1;   MCUCR = 0x80; // 允许外部并行扩展接口   init_devices();   /*   XMCRA = 0x44; //0x00 external memory   XMCRB = 0x01; // 释放PC7，作为通用I/O引脚使用     DDRC = 0xff; // PC7,PC6用于输出，（不影响PC0-PC5地址线）     PORTC = 0x00; // PC7,PC6输出0，（不影响PC0-PC5地址线）   */ XMCRA = 0x4A; //external memory //XMCRB = 0x01; // 释放PC7，作为通用I/O引脚使用   // DDRC = 0xff; // PC7,PC6用于输出，（不影响PC0-PC5地址线）   // PORTC = 0x00; // PC7,PC6输出0，（不影响PC0-PC5地址线）   //printf("this is uart1 "); Delayxms(50); //for(k=0;k

/* unsigned char  readram(unsigned int iaddr) { //unsigned char caddl,caddh; unsigned char cdatatemp=0;    RDH; WRH; ALEH; DDRA  = 0xFF; DDRC  = 0xFF; PORTC=iaddr>>8; PORTA=(unsigned char)iaddr; NOP(); ALEL;  //LATCH IT DDRA  = 0x00;//PORT INPUT   RDL; //2 send wr NOP(); cdatatemp=PINA; RDH; ALEH; return cdatatemp;    } void writeram(unsigned int iaddr, unsigned char ctemp) { //unsigned char caddl,caddh; unsigned char cdatatemp=0; RDH; WRH; ALEH; DDRA  = 0xFF; DDRC  = 0xFF; PORTC=iaddr>>8; PORTA=(unsigned char)iaddr; ALEL;//锁存A0-A7 WRL; PORTA=ctemp; NOP(); WRH; ALEH; return; } #define RAMSTARTADDR  0X1100 #define RAMENDADDR    0X90FF #define RAMLEN        32768 // 测试32KRAM void test_ram(void) { //1.首先写RAM 0x55 //2.读RAM是否为0X55，如果不是打印出16BITS地址 //3.写RAM0XAA， //4.读RAM是否为0XAA，如果不是打印出16BITS地址 //5.测试结束 unsigned char temp; unsigned int i; temp =0x55; //for(i=RAMSTARTADDR;i

#ifdef MCUBAUD9600 // UBRRL = (fosc / 16 / (baud + 1)) % 256;   // UBRRH = (fosc / 16 / (baud + 1)) / 256;   UCSR1B = 0x00; //disable while setting baud rate UCSR1A = 0x00; UCSR1C = 0x06; UBRR1L = 0x67; //set baud rate lo UBRR1H = 0x00; //set baud rate hi UCSR1B = 0x18; #else   UCSR1B = 0x00; //disable while setting baud rate UCSR1A = 0x00; UCSR1C = 0x06; UBRR1L = (F_CPU / 16 / (baud + 1)) % 256;//0x03;//0x08; //set baud rate lo UBRR1H = (F_CPU / 16 / (baud + 1)) / 256;//0x00; //set baud rate hi UCSR1B = 0x18;//0x98; #endif   } /* #pragma interrupt_handler int0_isr:2 void int0_isr(void) { //external interupt on INT0 } */ //call this routine to initialise all peripherals void init_devices(void) { //stop errant interrupts until set up CLI(); //disable all interrupts XDIV  = 0x00; //xtal divider port_init();   mapping_init(); watchdog_init(); uart1_init(); //External RAM will reside between 8000h - FFFFh. //There will be 2 wait states for both read and write. // MCUCR = 0x80; //EICRA = 0x03; //extended ext ints //EICRB = 0x00; //extended ext ints //EIMSK = 0x01; //TIMSK = 0x00; //timer interrupt sources //ETIMSK = 0x00; //extended timer interrupt sources SEI(); //re-enable interrupts //all peripherals are now initialised          }

t1=(c/256)%16; UDR1 = char2hex(t1); while(!(UCSR1A & 0x40)); UCSR1A |=0x40; t2=(c%256)/16;//templ&0xf0; //t2=t2>>8; UDR1 = char2hex(t2); while(!(UCSR1A & 0x40)); UCSR1A |=0x40; t2=(c%256)%16;//templ&0x0f; UDR1 = char2hex(t2); while(!(UCSR1A & 0x40)); UCSR1A |=0x40; } void sendchar1(char c) // 发送   { UDR1 = c; while(!(UCSR1A & 0x40)); UCSR1A |=0x40; } void sendint1( int c) // 发送   { UDR1 = (c&0xff00)>>8; while(!(UCSR1A & 0x40)); UCSR1A |=0x40; UDR1 = c&0xff; while(!(UCSR1A & 0x40)); UCSR1A |=0x40; } void sendstring1(unsigned char * txbuf) // 发送   { unsigned int j; for (j = 0; *txbuf; j++, txbuf++)sendchar1(*txbuf); //for(;*txbuf!='/0';txbuf++) } void port_init(void) { //PA AD0-AD7  地址 //PC AD8-AD15 PORTA = 0xFF; DDRA  = 0xFF; PORTC = 0xFF; //m103 output only DDRC  = 0x00; //PB4 NETRST O    PORTB = 0xFF; DDRB  = 0x10;    PORTD = 0xFF; DDRD  = 0x00; // PE0 RXD0   // PE1 TXD0 // PE4 NET_IRQ  i // PE5 INFRA_IRQ  i //   PORTE = 0xFF; DDRE  = 0x00;    PORTF = 0xFF; DDRF  = 0x00;    PORTG = 0x1F; DDRG  = 0x00; } //Watchdog initialisation // prescale: 2048K cycles void watchdog_init(void) { WDR(); //this prevents a timout on enabling //WDTCR = 0x0F; //WATCHDOG ENABLED - dont forget to issue WDRs /* reset WDT */ /* Write logical one to WDTOE and WDE */ //WDTCR |= (1

以下程序的结果是这个汗!!!!!! //ICC-AVR application builder : 2006-8-14 16:03:08 // Target : M128 // Crystal: 16.000Mhz //1.debug rs232 // #include #include #include #include //MCU时钟频率 #define F_CPU   16000000 //默认的系统BAUD #define baud    115200        #define MCUBAUD9600 1    //declare memory mapped variables #define txbuf1_head 0x1100 extern volatile unsigned char txbuf1[28415]; //define mappings void mapping_init(void) { asm(   ".area memory(abs) "   ".org 0x1100 "   " _txbuf1:: .blkb 28415 "   ".text " );    } //#define ext_PORT1 ((volatile unsigned char *)0x1100) //unsigned char *p=(unsigned char *)ext_PORT1; unsigned char testramtable[4]={0x00,0x55,0xaa,0x00}; //int COM; void Delay(void) { } void Delay1ms(void) {          unsigned int  i; for(i=0;i8; UDR1 = char2hex(t1); while(!(UCSR1A & 0x40)); UCSR1A |=0x40;

XMCRA = 0x40; //external memory XMCRB=0X00; #define txbuf1_head 0x1100 extern unsigned char txbuf1[256]; //define mappings void mapping_init(void) { asm(   ".area memory(abs) "   ".org 0x1100 "   " _txbuf1:: .blkb 256 "   ".text " ); } ram 现在可以读了,马上可以测试RAM了!

RAM读取错误图片！！