The Art of Hardware Architecture

1 The World of Metastability ..................................................................... 1 1.1 Introduction ........................................................................................ 1 1.2 Theory of Metastability ...................................................................... 1 1.3 Metastability Window ........................................................................ 3 1.4 Calculating MTBF ............................................................................. 3 1.5 Avoiding Metastability ....................................................................... 5 1.5.1 Using a Multi-stage Synchronizer ......................................... 6 1.5.2 Multi-stage Synchronizer Using Clock Boost Circuitry ........ 6 1.6 Metastability Test Circuitry ............................................................... 7 1.7 Types of Synchronizers ...................................................................... 8 1.8 Metastability/General Recommendations .......................................... 10 2 Clocks and Resets ..................................................................................... 11 2.1 Introduction ........................................................................................ 11 2.2 Synchronous Designs ......................................................................... 11 2.2.1 Avoid Using Ripple Counters ................................................ 12 2.2.2 Gated Clocks .......................................................................... 12 2.2.3 Double-Edged or Mixed Edge Clocking ................................ 13 2.2.4 Flip Flops Driving Asynchronous Reset of Another Flop ...................................................................... 13 2.3 Recommended Design Techniques .................................................... 14 2.3.1 Avoid Combinational Loops in Design .................................. 14 2.3.2 Avoid Delay Chains in Digital Logic ..................................... 16 2.3.3 Avoid Using Asynchronous Based Pulse Generator .............. 16 2.3.4 Avoid Using Latches .............................................................. 17 2.3.5 Avoid Using Double-Edged Clocking ................................... 20 2.4 Clocking Schemes .............................................................................. 22 2.4.1 Internally Generated Clocks .................................................. 22 2.4.2 Divided Clocks ....................................................................... 24 2.4.3 Ripple Counters ..................................................................... 25 2.4.4 Multiplexed Clocks ................................................................ 25 2.4.5 Synchronous Clock Enables and Gated Clocks ..................... 26 xii Contents 2.5 Clock Gating Methodology ................................................................ 28 2.5.1 Latch Free Clock Gating Circuit ............................................ 28 2.5.2 Latch Based Clock Gating Circuit ......................................... 30 2.5.3 Gating Signals ........................................................................ 32 2.5.4 Data Path Re-ordering to Reduce Switching Propagation ........................................................... 32 2.6 Reset Design Strategy ........................................................................ 32 2.6.1 Design with Synchronous Reset ............................................ 33 2.6.2 Design with Asynchronous Reset .......................................... 36 2.6.3 Flip Flops with Asynchronous Reset and Asynchronous Set ............................................................ 38 2.6.4 Asynchronous Reset Removal Problem ................................. 40 2.6.5 Reset Synchronizer ................................................................ 40 2.6.6 Reset Glitch Filtering ............................................................. 42 2.7 Controlling Clock Skew ..................................................................... 42 2.7.1 Short Path Problem ................................................................ 43 2.7.2 Clock Skew and Short Path Analysis ..................................... 44 2.7.3 Minimizing Clock Skew ........................................................ 46 References ................................................................................................... 49 3 Handling Multiple Clocks........................................................................ 51 3.1 Introduction ........................................................................................ 51 3.2 Multiple Clock Domains .................................................................... 51 3.3 Problems with Multiple Clock Domains Design ............................... 51 3.3.1 Setup Time and Hold Time Violation .................................... 53 3.3.2 Metastability .......................................................................... 53 3.4 Design Tips for Efficient Handling of a Design with Multiple Clocks .................................................................................. 54 3.4.1 Clock Nomenclature .............................................................. 54 3.4.2 Design Partitioning ................................................................ 55 3.4.3 Clock Domain Crossing ......................................................... 55 3.5 Synchronous Clock Domain Crossing ............................................... 58 3.5.1 Clocks with the Same Frequency and Zero Phase Difference .................................................................... 59 3.5.2 Clocks with the Same Frequency and Constant Phase Difference .................................................................... 59 3.5.3 Clocks with the Different Frequency and Variable Phase Difference .................................................................... 60 3.6 Handshake Signaling Method ............................................................ 64 3.6.1 Requirements for Handshake Signaling ................................. 65 3.6.2 Disadvantages of Handshake Signaling ................................. 66 3.7 Data Transfer Using Synchronous FIFO ........................................... 66 3.7.1 Synchronous FIFO Architecture ............................................ 67 xiii Contents 3.7.2 Working of Synchronous FIFO .............................................. 68 3.8 Asynchronous FIFO (or Dual Clock FIFO) ....................................... 69 3.8.1 Avoid Using Binary Counters for the Pointer Implementation ...................................................................... 70 3.8.2 Use Gray Coding Instead of Binary for the Counters ............ 71 3.8.3 Gray Code Implementation of FIFO Pointers ........................ 74 3.8.4 FIFO Full and FIFO Empty Generation ................................. 79 3.8.5 Dual Clock FIFO Design ....................................................... 82 References ................................................................................................... 86 4 Clock Dividers........................................................................................... 87 4.1 Introduction ........................................................................................ 87 4.2 Synchronous Divide by Integer Value ............................................... 87 4.3 Odd Integer Division with 50% Duty Cycle ...................................... 88 4.4 Non-integer Division (with a Non 50% Duty Cycle) ........................ 90 4.4.1 Divide by 1.5 with Non 50% Duty Cycle .............................. 90 4.4.2 Counter Implementation for Divide by 4.5 (Non 50% Duty Cycle) .......................................................... 91 4.5 Alternate Approach for Divide by N .................................................. 92 4.5.1 LUT Implementation for Divide by 1.5 ................................. 93 Reference .................................................................................................... 93 5 Low Power Design..................................................................................... 95 5.1 Introduction ........................................................................................ 95 5.2 Sources of Power Consumption ......................................................... 95 5.3 Power Reduction at Different Levels of Design Abstraction ............. 96 5.4 System Level Power Reduction ......................................................... 98 5.4.1 System on Chip (SoC) Approach ........................................... 98 5.4.2 Hardware/Software Partitioning ............................................ 98 5.4.3 Low Power Software .............................................................. 101 5.4.4 Choice of Processor ............................................................... 102 5.5 Architecture Level Power Reduction ................................................. 102 5.5.1 Advanced Clock Gating ......................................................... 103 5.5.2 Dynamic Voltage and Frequency Scaling (DVFS) ................ 104 5.5.3 Cache Based Architecture ...................................................... 105 5.5.4 Log FFT Architecture ............................................................ 106 5.5.5 Asynchronous (Clockless) Design ......................................... 106 5.5.6 Power Gating.......................................................................... 108 5.5.7 Multi-threshold Voltage ......................................................... 111 5.5.8 Multi-supply Voltage.............................................................. 112 5.5.9 Gate Memory Power .............................................................. 112 5.6 Register Transfer Level (RTL) Power Reduction .............................. 113 5.6.1 State Machine Encoding and Decomposition ........................ 113 5.6.2 Binary Number Representation .............................................. 114 xiv Contents 5.6.3 Basic Gated Clock .............................................................. 115 5.6.4 One Hot Encoded Multiplexer ........................................... 117 5.6.5 Removing Redundant Transactions ................................... 118 5.6.6 Resource Sharing ............................................................... 119 5.6.7 Using Ripple Counters for Low Power .............................. 121 5.6.8 Bus Inversion ..................................................................... 124 5.6.9 High Activity Nets ............................................................. 124 5.6.10 Enabling-Disabling Logic Clouds ...................................... 125 5.7 Transistor Level Power Reduction ................................................... 126 5.7.1 Technology Level ............................................................... 126 5.7.2 Layout Optimization .......................................................... 127 5.7.3 Substrate Biasing ............................................................... 127 5.7.4 Reduce Oxide Thickness .................................................... 127 5.7.5 Multi-oxide Devices ........................................................... 127 5.7.6 Minimizing Capacitance by Custom Design ..................... 128 References ................................................................................................... 128 6 The Art of Pipelining................................................................................ 129 6.1 Introduction ...................................................................................... 129 6.2 Factors Affecting the Maximum Frequency of Clock ..................... 129 6.2.1 Clock Skew ........................................................................ 131 6.2.2 Clock Jitter ......................................................................... 131 6.3 Pipelining ......................................................................................... 133 6.4 Pipelining Explained – A Real Life Example .................................. 136 6.5 Performance Increase from Pipelining ............................................ 137 6.6 Implementation of DLX Instruction ................................................ 140 6.7 Effect of Pipelining on Throughput ................................................. 144 6.8 Pipelining Principles ........................................................................ 145 6.9 Pipelining Hazards ........................................................................... 146 6.9.1 Structural Hazards ............................................................. 146 6.9.2 Data Hazards ...................................................................... 147 6.9.3 Control Hazards ................................................................. 150 6.9.4 Other Hazards .................................................................... 151 6.10 Pipelining in ADC – An Example ................................................... 152 References ................................................................................................... 153 7 Handling Endianness................................................................................ 155 7.1 Introduction ...................................................................................... 155 7.2 Definition ......................................................................................... 155 7.3 Little-Endian or Big-Endian: Which Is better? ................................ 157 7.4 Issues Dealing with Endianess Mismatch ........................................ 158 7.5 Accessing 32 Bit Memory ............................................................... 160 7.6 Dealing with Endianness Mismatch ................................................ 161 xv Contents 7.6.1 Preserve Data Integrity (Data Invariance) .............................. 161 7.6.2 Address Invariance ................................................................. 163 7.6.3 Software Byte Swapping ........................................................ 166 7.7 Endian Neutral code ........................................................................... 167 7.8 Endian-Neutral Coding Guidelines .................................................... 167 References ................................................................................................... 168 8 Deboucing Techniques.............................................................................. 169 8.1 Introduction ........................................................................................ 169 8.2 Behavior of a Switch .......................................................................... 170 8.3 Switch Types ...................................................................................... 171 8.4 De-bouncing Techniques ................................................................... 172 8.4.1 RC De-bouncer ...................................................................... 172 8.4.2 Hardware De-bouncers .......................................................... 176 8.4.3 Software De-bouncing ........................................................... 177 8.4.4 De-bouncing Guidelines ........................................................ 179 8.4.5 De-bouncing on Multiple Inputs ............................................ 180 8.5 Existing Solutions .............................................................................. 181 9 Design Guidelines for EMC Performance.............................................. 183 9.1 Introduction ........................................................................................ 183 9.2 Definition ........................................................................................... 183 9.3 EMI Theory and Relationship with Current and Frequency .............. 185 9.4 EMI Regulations, Standards and Certification ................................... 186 9.5 Factors Affecting IC Immunity Performance .................................... 187 9.5.1 Microcontroller as Noise Source ........................................... 187 9.5.2 Other Factors Affecting EMC ................................................ 188 9.5.3 Noise Carriers ........................................................................ 189 9.6 Techniques to Reduce EMC/EMI ...................................................... 189 9.6.1 System Level Techniques ....................................................... 190 9.6.2 Board Level Techniques ......................................................... 192 9.6.3 Microcontroller Level Techniques ......................................... 201 9.6.4 Software Level Techniques .................................................... 205 9.6.5 Other Techniques ................................................................... 212 9.7 Summary ............................................................................................ 213 References ................................................................................................... 214 References........................................................................................................ 215 Index................................................................................................................. 219

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