晤。。。真的没人吗

这是0-5 counter，Q用来表示有没有数到5 library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity count_0_to_5 is port (clk : in std_logic;       count : buffer std_logic_vector(2 downto 0);       reset_n :in std_logic;                 Q: out std_logic       ); end count_0_to_5; architecture Behavior of count_0_to_5 is begin process(clk,reset_n) begin      if(rising_edge(clk)) then     if (count="101")then             count'0');          else count

这是tb的 LIBRARY ieee; USE ieee.std_logic_1164.ALL; USE ieee.std_logic_unsigned.all; ENTITY count_0_to_5_tb IS END count_0_to_5_tb; ARCHITECTURE behavior OF count_0_to_5_tb IS         COMPONENT count_0_to_5       PORT(clk : IN  std_logic;          count : buffer  std_logic_vector(2 downto 0);          reset_n : IN  std_logic;                         Q: out std_logic         );     END COMPONENT;    signal clk : std_logic := '0';    signal reset_n : std_logic := '1';    signal count : std_logic_vector(2 downto 0);         signal Q: std_logic;        constant clk_period : time := 1 ms; BEGIN        uut: count_0_to_5 PORT MAP (           clk => clk,           count => count,           reset_n => reset_n,                          Q => Q         );              clk_process :process    begin         clk

多谢

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