不好意思，程序在这
#include "sam.h"
#include "samR21G18A.h"
#define _BV(bit) (1 Group[0].WRCONFIG.reg =( PORT_WRCONFIG_MASK & (PORT_WRCONFIG_PMUXEN | PORT_WRCONFIG_PULLEN | PORT_WRCONFIG_INEN | PORT_WRCONFIG_PMUX(MUX_PA28A_EIC_EXTINT8) | PORT_WRCONFIG_WRPMUX | PORT_WRCONFIG_WRPINCFG | _BV(12) | PORT_WRCONFIG_HWSEL ));
REG_PORT_OUT0 |= _BV(28); // disable the PA28, set to high voltage (1)
//PORT->Group[0].PMUX[13].reg = 0x0;
REG_PORT_PMUX0_13 = PORT_PMUX_PMUXE_A;
PORT->Group[0].PINCFG[28].reg = PORT_PINCFG_PMUXEN | PORT_PINCFG_PULLEN;
// power manager
REG_PM_APBBMASK |= _BV(3); // enable CLK_PORT_APB, pp. 333
// Generic Clock controller
REG_EIC_CTRL &= ~_BV(1); // disable EIC
while( (REG_EIC_STATUS & (_BV(7))) == 1 ); // bit 7: check Synchronization Busy Status. pp.340
REG_EIC_CTRL |= _BV(0); // software reset EIC
while( (REG_EIC_STATUS & (_BV(7))) == 1 ); // bit 7: check Synchronization Busy Status. pp.340
REG_PM_APBAMASK |= _BV(6); // enable CLK_EIC_APB, pp. 333
// the default GCLK0 (GCLK_MAIN) is used for IO
REG_GCLK_GENDIV = 0x100; // bit 31-0: 0000 0000 0000 0000 0000 0001 0000 0000, do a 32-bit write with all configurations and the ID. pp.109
while( (REG_GCLK_STATUS & (_BV(7))) == 1 ); // bit 7: check Synchronization Busy Status. pp.100
// Bit 21: Enable Run in Standby, Bit 20: Disable Divide Selection, Bit 19: Disable Output, Bit 18: clear GCLK_IO to zero
// Bit 17: Improve Duty Cycle, Bit 16: Enable Generic Clock Generator, Bit 12-8: Select OSC8M, Bit 3-0: Select GCLKGEN0
REG_GCLK_GENCTRL = 0x00230600; // bit 31-0: 0000 0000 0010 0011 0000 0110 0000 0000. do a 32-bit write with all configurations and the ID. pp.105
while( (REG_GCLK_STATUS & (_BV(7))) == 1 ); // bit 7: check Synchronization Busy Status. pp.100
// bit 15: Disable Lock Write, Bit 14: Enable Clock, Bit 11-8: Choose GCLKGEN5, Bit 5-0: Choose GCLK_EIC
REG_GCLK_CLKCTRL = 0x4005; // bit 15-0: 0100 0000 0000 0101. do a 16-bit write with all configurations and the ID. pp.101
// EIC configuration registers
while (EIC->CTRL.bit.SWRST | EIC->STATUS.bit.SYNCBUSY);
//REG_EIC_CTRL |= _BV(1); // enable EIC
REG_EIC_CONFIG2 |= EIC_CONFIG_FILTEN4 | EIC_CONFIG_SENSE4_BOTH;
//REG_EIC_CONFIG2 |= _BV(19); // bit 19 FILTEN28: enable filter of IO 28 pp. 348
//REG_EIC_CONFIG2 = (0x1
Microchip MCU