boot在的代码
SLEEPDATA_BASE_VIRTUAL EQU 0xac058000 ; keep in sync w/ config.bib
SLEEPDATA_BASE_PHYSICAL EQU 0x3c058000
WAKEUP_POWER_OFF
;在Stepldr中
; Resume handler code.
; Release SCLKn after wake-up from the POWER_OFF mode.
ldr r1,=MISCCR
ldr r0,[r1]
bic r0,r0,#(7SCLK, SCKE:L->H
str r0,[r1]
; Set up the memory control registers.
;
; add r0, pc, #SMRDATA - (. + 8)
; ldr r1, =BWSCON ; BWSCON Address.
; add r2, r0, #52 ; End address of SMRDATA.
ldr r0,=SMRDATA
ldr r1,=BWSCON ;BWSCON Address
add r2, r0, #52 ;End address of SMRDATA
3
ldr r3, [r0], #4
str r3, [r1], #4
cmp r2, r0
bne %B3
mov r0, #0x2000
4
subs r0, r0, #1
bne %B4
;------------------------------------------------------------------------------
; Recover Process : Starting Point
;
; 1. Checksum Calculation saved Data
ldr r5, =SLEEPDATA_BASE_PHYSICAL ; pointer to physical address of reserved Sleep mode info data structure //注意是指向一个 "唤醒模式信息"的结构体的地址
mov r3, r5 ; pointer for checksum calculation
ldr r2, =0x0
ldr r0, =(SLEEPDATA_SIZE-1) ; get size of data structure to do checksum on
; ldr r0, =SLEEPDATA_SIZE
50
ldr r1, [r3], #4 ; pointer to SLEEPDATA
and r1, r1, #0x1
mov r1, r1, ROR #31
add r2, r2, r1
subs r0, r0, #1 ; dec the count
bne %b50 ; loop till done
ldr r0,=GSTATUS3
ldr r3, [r0] ; get the Sleep data checksum from the Power Manager Scratch pad register
cmp r2, r3 ; compare to what we saved before going to sleep
bne BringUpWinCE ; bad news - do a cold boot
ldr r0,=GPFDAT ;灯灭
ldr r1,=0x10
str r1,[r0]
b .
; 2. MMU Enable
ldr r10, [r5, #SleepState_MMUDOMAIN] ; load the MMU domain access info
ldr r9, [r5, #SleepState_MMUTTB] ; load the MMU TTB info
ldr r8, [r5, #SleepState_MMUCTL] ; load the MMU control info
ldr r7, [r5, #SleepState_WakeAddr ] ; load the LR address
nop
nop
nop
nop
nop
; if software reset
mov r1, #0
teq r1, r7
bne %f60
b BringUpWinCE
; wakeup routine
60 mcr p15, 0, r10, c3, c0, 0 ; setup access to domain 0
mcr p15, 0, r9, c2, c0, 0 ; PT address
mcr p15, 0, r0, c8, c7, 0 ; flush I+D TLBs
mcr p15, 0, r8, c1, c0, 0 ; restore MMU control
; 3. Jump to Kernel Image's fw.s (Awake_address)
mov pc, r7 ; jump to new VA (back up Power management stack)
nop
BringUpWinCE
; bad news, data lose, bring up wince again
mov r0, #2
ldr r1, =GSTATUS2
str r0, [r1]
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config.bib
#define NKNAME NK
; NK Start address
#define NKSTART 8C200000
#define NKLEN 01D00000
#define RAMSTART 8E000000 ;8E000000
#define RAMLEN 02000000 ;01F00000
$(NKNAME) $(NKSTART) $(NKLEN) RAMIMAGE
RAM $(RAMSTART) $(RAMLEN) RAM
; NK 80040000 01EB0000 RAMIMAGE
; RAM 8c200000 01C00000 RAM
; Common RAM areas
AUD_DMA 8c002000 00002000 RESERVED
DRV_GLB 8c010000 00010000 RESERVED
DBGSER_DMA 8c022000 00002000 RESERVED
SER_DMA 8c024000 00002000 RESERVED
IR_DMA 8c026000 00002000 RESERVED
SD_DMA 8c028000 00008000 RESERVED
EDBG 8c030000 00020000 RESERVED
CPXIPCHAIN 8c050000 00008000 RESERVED
SLEEP_BUFF 8c058000 00004000 RESERVED
DISPLAY 8c100000 00100000 RESERVED
CONFIG
COMPRESSION=ON
KERNELFIXUPS=ON
IF IMGPROFILER
PROFILE=ON
ENDIF
IF IMGPROFILER !
PROFILE=OFF
ENDIF
ROMFLAGS=0
ROMSTART=$(NKSTART)
ROMWIDTH=32
ROMSIZE=$(NKLEN)
; ROMSIZE=01EB0000
;#define CHAIN_ADDRESS 81E40000
; CHAIN $(CHAIN_ADDRESS) 00001000 RESERVED
; pdwXIPLoc 00000000 $(CHAIN_ADDRESS) FIXUPVAR
; NK 80040000 01E00000 RAMIMAGE
; CHAIN 81E40000 00001000 RESERVED
; DRIVERS 81E41000 001BF000 RAMIMAGE
; RESERVE 8df00000 00080000
; RAM 8c200000 01D00000 RAM
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map.a
; Mapped for S3C2400X01
EXPORT OEMAddressTable[DATA]
OEMAddressTable
;;;-------------------------------------------------------------
;;; Virt Addr Phys Addr MB
;;;-------------------------------------------------------------
DCD 0x80000000, 0x02000000, 30 ; 30 MB SROM(SRAM/ROM) BANK 0
DCD 0x82000000, 0x08000000, 32 ; 32 MB SROM(SRAM/ROM) BANK 1
DCD 0x84000000, 0x10000000, 32 ; 32 MB SROM(SRAM/ROM) BANK 2
DCD 0x86000000, 0x18000000, 32 ; 32 MB SROM(SRAM/ROM) BANK 3
DCD 0x88000000, 0x20000000, 32 ; 32 MB SROM(SRAM/ROM) BANK 4
DCD 0x8A000000, 0x28000000, 32 ; 32 MB SROM(SRAM/ROM) BANK 5
DCD 0x8C000000, 0x30000000, 64 ; 64 MB DRAM BANK 0,1
DCD 0x90800000, 0x48000000, 1 ; Memory control register
DCD 0x90900000, 0x49000000, 1 ; USB Host register
DCD 0x90A00000, 0x4A000000, 1 ; Interrupt Control register
DCD 0x90B00000, 0x4B000000, 1 ; DMA control register
DCD 0x90C00000, 0x4C000000, 1 ; Clock & Power register
DCD 0x90D00000, 0x4D000000, 1 ; LCD control register
DCD 0x90E00000, 0x4E000000, 1 ; NAND flash control register
DCD 0x91000000, 0x50000000, 1 ; UART control register
DCD 0x91100000, 0x51000000, 1 ; PWM timer register
DCD 0x91200000, 0x52000000, 1 ; USB device register
DCD 0x91300000, 0x53000000, 1 ; Watchdog Timer register
DCD 0x91400000, 0x54000000, 1 ; IIC control register
DCD 0x91500000, 0x55000000, 1 ; IIS control register
DCD 0x91600000, 0x56000000, 1 ; I/O Port register
DCD 0x91700000, 0x57000000, 1 ; RTC control register
DCD 0x91800000, 0x58000000, 1 ; A/D convert register
DCD 0x91900000, 0x59000000, 1 ; SPI register
DCD 0x91A00000, 0x5A000000, 1 ; SD Interface register
DCD 0x92000000, 0x00000000, 2 ; 2 MB SROM(SRAM/ROM) BANK 0
DCD 0x00000000, 0x00000000, 0 ; End of Table (MB MUST BE ZERO!)
END
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stm32/stm8