MCASP_ConfigGbl configGbl =
{
0x00000000, /* PFUNC - All pins as McASP */
// 0x1c000002, //AXR1 out,AFSX AHCLKX ACLKX out,others are inputs
0x00000080, /* PDIR - AXR1 out,others are inputs */
0x00000000, /* DITCTL - DIT mode disable */
0x00000003, /* DLBCTL - Loopback disabled */
0x00000000 /* AMUTE - Never drive AMUTE */
};
MCASP_ConfigRcv configRcv =
{
0xffffffff, /* RMASK - Use all 32 bits */
0x000180f0, //1-bit delay,MSB first, 32-bit slots, DAT bus,
0x00000111, //AFSRCTL 2-slot word frame sync, ext FS,falling
// 0x00000113, //AFSRCTL 2-slot word frame sync, in FS,falling
0x00000000, /* ACLKRCTL - Sample on rising CLK, divide by 1, ext CLK */
// 0x00000020, // ACLKRCTL - Sample on rising CLK, divide by 1, in CLK
0x00000000, /* AHCLKRCTL - External HCLK */
// 0x0000c031, //AHCLKRCTL - in HCLK, falling AHCLK, divide by 50
0x00000003, /* RTDM - Slots 0 1 are active */
0x00000000, /* RINTCTL - No interrupts */
0x00000000 /* RCLKCHK - Not used */
};
MCASP_ConfigXmt configXmt =
{
0xffffffff, /* XMASK - Use all 32 bits */
0x000180f0, //1-bit delay,MSB first, 32-bit slots, DAT bus,
//0x00000113, //AFSXCTL-2-slot word frame sync, in FS ,falling
0x00000111, //AFSXCTL-2-slot word frame sync, ext FS ,falling
// 0x000000e0, /* ACLKXCTL - Sample on falling CLK, async,divide by 1, in CLK */
//0x000000c0, /* ACLKXCTL - Sample on falling CLK, async,divide by 1, ext CLK */
0x00000080, /* ACLKXCTL - Sample on falling CLK, sync,divide by 1, ext CLK */
// 0x0000c031, /* AHCLKXCTL - in HCLK , falling , 50 divider*/
0x00000000, /* AHCLKXCTL - External HCLK */
0x00000003, /* XTDM - Slots 0 1 are active */
0x00000000, /* XINTCTL - No interrupts */
0x00000000 /* XCLKCHK - Not used */
};
MCASP_ConfigSrctl configSrctl =
{ //SRCTL,
0x00000000, /* SRCTL0 - Inactive */
0x00000000, /* SRCTL1 - Inactive*/
0x00000000, /* SRCTL2 - Inactive */
0x00000000, /* SRCTL3 - Inactive */
0x00000000, /* SRCTL4 - Inactive */
0x00000000, /* SRCTL5 - Inactive */
0x0000000e, /* SRCTL6 - Receive, active high */
0x0000000d /* SRCTL7 - Transmit, active high */
};
MCASP_configRcv(hMcASP, &configRcv);
for(i=0;i
FPGA/CPLD