library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_ARITH.all;
use IEEE.STD_LOGIC_UNSIGNED.all;
ENTITY LS192 IS
port (clr,set,cp1,cp2 : in STD_LOGIC;
q : in STD_LOGIC_VECTOR(3DOWNTO 0);
d: out STD_LOGIC_VECTOR(3DOWNTO 0);
jinwei:out STD_LOGIC;
jiewei:out STD_LOGIC);
end ENTITY LS192 ;
architecture behav of LS192 is
signal conut1_4 : STD_LOGIC_VECTOR(3DOWNTO 0);
signal conut2_4 : STD_LOGIC_VECTOR(3DOWNTO 0);
signal a1 : STD_LOGIC;
signal a2 : STD_LOGIC;
begin
process( clr,set,cp1,q) --jifaqi
begin
if(clr='1')then --qingling
conut1_4