ENTITY Speakera IS
PORT ( clk : IN STD_LOGIC ; --待分频时钟12M Hz
e : IN std_logic_vector(14 downto 0);--INTEGER RANGE 0 TO 16#7FF# ;--分频预置数输入
f : OUT STD_LOGIC ) ; --发声输出
END ;
--****************************************************
ARCHITECTURE one OF Speakera IS
SIGNAL q : STD_LOGIC_vector(14 downto 0) ;
SIGNAL c1,c2 : STD_LOGIC ;
BEGIN
PROCESS(clk)
BEGIN
IF e="000000000000000" THEN
c1