static BOOL LCDCInitialize(int width, int height, int bpp)
{
BOOL rc = TRUE;
UINT32 pixelBytes;
UINT32 uLCDRefClk;
CSP_LCDC_REGS *pLCDC;
BSP_ARGS *pBspArgs = (BSP_ARGS *)OALPAtoUA(IMAGE_SHARE_ARGS_RAM_PA_START);
pixelBytes = LCDC_PIXEL_SIZE_BYTES(bpp);
pLCDC = (CSP_LCDC_REGS *)OALPAtoUA(CSP_BASE_REG_PA_LCDC);
// Disable LCDC clock
LCDCEnable(FALSE);
// Disable self refresh
pLCDC->RMCR &= ~CSP_BITFMASK(LCDC_RMCR_SELF_REF);
pLCDC->SSAR = IMAGE_SHARE_FRAMEBUFFER_RAM_PA_START;
pLCDC->SR = CSP_BITFVAL(LCDC_SR_YMAX, BSP_PREF_DISPLAY_HEIGHT) |
CSP_BITFVAL(LCDC_SR_XMAX, (BSP_PREF_DISPLAY_WIDTH / 16) ) |
CSP_BITFVAL(LCDC_SR_BUSSIZE, LCDC_SR_BUSSIZE_32BIT);
pLCDC->VPWR = BSP_PREF_DISPLAY_WIDTH / (4 / pixelBytes);
// disable cursor
pLCDC->CPR = CSP_BITFVAL(LCDC_CPR_OP, LCDC_CPR_OP_DISABLE) |
CSP_BITFVAL(LCDC_CPR_CC, LCDC_CPR_CC_DISABLED);
// Disable cursor blink, all settings default
pLCDC->CWHBR = CSP_BITFVAL(LCDC_CWHBR_BK_EN, LCDC_CWHBR_BK_EN_DISABLE) |
CSP_BITFVAL(LCDC_CWHBR_CW, LCDC_CWHBR_CW_CURSOR_DISABLED) |
CSP_BITFVAL(LCDC_CWHBR_CH, LCDC_CWHBR_CH_CURSOR_DISABLED) |
CSP_BITFVAL(LCDC_CWHBR_BD, LCDC_CWHBR_BD_MAX_DIV);
// CCMR: Default as on reset
pLCDC->CCMR = 0;
// Set Pixel polarity bit since color is inverted in lcd board.
uLCDRefClk = pBspArgs->clockFreq[DDK_CLOCK_SIGNAL_PERDIV3];
#ifdef VGA_DISPLAY
OALMSG(1, (TEXT("VGA_DISPLAY defined\r\n")));
#else
OALMSG(1, (TEXT("VGA_DISPLAY not defined\r\n")));
#endif
pLCDC->PCR =
#ifdef VGA_DISPLAY
CSP_BITFVAL(LCDC_PCR_SHARP, LCDC_PCR_SHARP_DISABLE) |
CSP_BITFVAL(LCDC_PCR_PIXPOL, LCDC_PCR_PIXPOL_ACTIVE_HIGH) |
#else
CSP_BITFVAL(LCDC_PCR_SHARP, LCDC_PCR_SHARP_ENABLE) |
// CSP_BITFVAL(LCDC_PCR_PIXPOL, LCDC_PCR_PIXPOL_ACTIVE_LOW) |
CSP_BITFVAL(LCDC_PCR_PIXPOL, LCDC_PCR_PIXPOL_ACTIVE_HIGH) |
#endif
CSP_BITFVAL(LCDC_PCR_SCLKSEL, LCDC_PCR_SCLKSEL_ENABLE) |
CSP_BITFVAL(LCDC_PCR_ACDSEL, LCDC_PCR_ACDSEL_USE_LPHSYNC) |
CSP_BITFVAL(LCDC_PCR_REV_VS, LCDC_PCR_REV_VS_NORMAL) |
CSP_BITFVAL(LCDC_PCR_SWAP_SEL, LCDC_PCR_SWAP_SEL_16BPP) |
CSP_BITFVAL(LCDC_PCR_END_SEL, LCDC_PCR_END_SEL_LITTLE_ENDIAN) |
CSP_BITFVAL(LCDC_PCR_SCLKIDLE, LCDC_PCR_SCLKIDLE_DISABLE) |
CSP_BITFVAL(LCDC_PCR_OEPOL, LCDC_PCR_OEPOL_ACTIVE_LOW) |
CSP_BITFVAL(LCDC_PCR_CLKPOL, LCDC_PCR_CLKPOL_NEG_EDGE) |
CSP_BITFVAL(LCDC_PCR_LPPOL, LCDC_PCR_LPPOL_ACTIVE_LOW) |
CSP_BITFVAL(LCDC_PCR_FLMPOL, LCDC_PCR_FLMPOL_ACTIVE_HIGH) |
CSP_BITFVAL(LCDC_PCR_PBSIZ, LCDC_PCR_PBSIZ_8BIT) |
CSP_BITFVAL(LCDC_PCR_COLOR, LCDC_PCR_COLOR_COLOR) |
CSP_BITFVAL(LCDC_PCR_TFT, LCDC_PCR_TFT_ACTIVE) |
CSP_BITFVAL(LCDC_PCR_PCD, LCDC_PCD_VALUE(uLCDRefClk, BSP_PIXEL_CLOCK_FREQ));
switch(bpp)
{
case 1:
pLCDC->PCR |= CSP_BITFVAL(LCDC_PCR_BPIX, LCDC_PCR_BPIX_1BPP);
break;
case 2:
pLCDC->PCR |= CSP_BITFVAL(LCDC_PCR_BPIX, LCDC_PCR_BPIX_2BPP);
break;
case 4:
pLCDC->PCR |= CSP_BITFVAL(LCDC_PCR_BPIX, LCDC_PCR_BPIX_4BPP);
break;
case 8:
pLCDC->PCR |= CSP_BITFVAL(LCDC_PCR_BPIX, LCDC_PCR_BPIX_8BPP);
break;
case 12:
pLCDC->PCR |= CSP_BITFVAL(LCDC_PCR_BPIX, LCDC_PCR_BPIX_12BPP);
break;
case 16:
pLCDC->PCR |= CSP_BITFVAL(LCDC_PCR_BPIX, LCDC_PCR_BPIX_16BPP);
break;
case 18:
pLCDC->PCR |= CSP_BITFVAL(LCDC_PCR_BPIX, LCDC_PCR_BPIX_18BPP);
break;
default:
goto cleanup;
}
pLCDC->HCR = CSP_BITFVAL(LCDC_HCR_H_WIDTH, 10) |
CSP_BITFVAL(LCDC_HCR_H_WAIT_1, 8) |
CSP_BITFVAL(LCDC_HCR_H_WAIT_2, 0);
pLCDC->VCR = CSP_BITFVAL(LCDC_VCR_V_WIDTH, 2) |
CSP_BITFVAL(LCDC_VCR_V_WAIT_1, 3) |
CSP_BITFVAL(LCDC_VCR_V_WAIT_2, 4) ;
pLCDC->PCR =0xFA6000C3;
pLCDC->HCR =0x28000400;
pLCDC->VCR =0x08000304;
// POR: 0 as reset default
pLCDC->POR = CSP_BITFVAL(LCDC_POR_POR, 0);
pLCDC->SCR = CSP_BITFVAL(LCDC_SCR_GRAY1, 0) |
CSP_BITFVAL(LCDC_SCR_GRAY2, 0) |
CSP_BITFVAL(LCDC_SCR_REV_TOGGLE_DELAY, 3) |
CSP_BITFVAL(LCDC_SCR_CLS_RISE_DELAY, 18) |
CSP_BITFVAL(LCDC_SCR_PS_RISE_DELAY, 1);
// Enable contrast for backlight control. Initialize to half power
pLCDC->PCCR = CSP_BITFVAL(LCDC_PCCR_PW, LCDC_PCCR_PW_MAX) |
CSP_BITFVAL(LCDC_PCCR_CC_EN, LCDC_PCCR_CC_EN_ENABLE) |
CSP_BITFVAL(LCDC_PCCR_SCR, LCDC_PCCR_SCR_PIXELCLK) |
CSP_BITFVAL(LCDC_PCCR_LDMSK, LCDC_PCCR_LDMSK_DISABLE) |
CSP_BITFVAL(LCDC_PCCR_CLS_HI_WIDTH, 169);
// Settings for heavily loaded bus with SDRAM access.
// dynamic burst, High mark = 3, low mark = 1D (best setting after testing)
pLCDC->DCR = CSP_BITFVAL(LCDC_DCR_BURST, LCDC_DCR_BURST_DYNAMIC) |
CSP_BITFVAL(LCDC_DCR_HM, 0x03) |
CSP_BITFVAL(LCDC_DCR_TM, 0x08);
// Set for interrupt on output of last data to panel, end of graphic window
pLCDC->ICR = CSP_BITFVAL(LCDC_ICR_GW_INT_CON, LCDC_ICR_GW_INT_CON_END) |
CSP_BITFVAL(LCDC_ICR_INTSYN, LCDC_ICR_INTSYN_PANEL) |
CSP_BITFVAL(LCDC_ICR_INTCON, LCDC_ICR_INTCON_BOF);
// Disable All interrupts
pLCDC->IER = 0;
// Setup graphic window DMA
// Don't change unless primary buffer DMA settings are changed
pLCDC->GWDCR = CSP_BITFVAL(LCDC_GWDCR_GWBT, LCDC_GWDCR_GWBT_DYNAMIC) |
CSP_BITFVAL(LCDC_GWDCR_GWHM, 0x02) |
CSP_BITFVAL(LCDC_GWDCR_GWTM, 0x10);
// Disable graphic window.
pLCDC->GWCR = CSP_BITFVAL(LCDC_GWCR_GWE, 0);
// We're done
rc = TRUE;
cleanup:
OALMSG(!rc, (TEXT("LCDCInitialize: rc (%d)\r\n"), rc));
return rc;
}
#else
stm32/stm8