qingfengmingyue 发表于 2015-9-26 17:22 留个联系方式，可以吗？

现在已经不用这个板子了，当时就是比赛项目玩玩的，交流技术可以加QQ824340139

王耀天下 发表于 2015-9-19 15:13 楼主能不能请您说一下完整的从申请到实际使用SDAccel的方法啊，为什么我在各个地方都下不到这个环境。。。 ...

找FAE要

多次测量取中值最稳妥。

gaoyuan1117 发表于 2015-8-10 13:17 我也想知道opencl license怎么申请

1. 找骏龙或者艾瑞 2. 参加各种Altera比赛 3. 等网上有大神破解

我现在用的板子一个外设都没有，只有BLASTER下载线接口。 其实有了SignalTap，外设都是浮云。

fxiaonp 发表于 2015-8-6 17:24 请问博主，OpenCL SDK可以和传统的RTL设计放到一个design一起编译吗？

OpenCL SDK编译后的quartus工程可以打开，但同传统RTL的接口却是个问题，Altera并没给出具体信号连接情况。

qq365317289 发表于 2015-7-23 20:17 楼主，请问你有没有将Stratix V 上的opencl跑出来 ？ 我输入命令aoc program acl0 hello_world.cl 编译时 ...

我用的不是DE5，没法对比:~o

本帖最后由 zhaoyongke 于 2015-8-7 10:02 编辑

chenzhufly 发表于 2015-8-5 19:44 呀  榜上有名

恭喜柱版，活跃了社区，贡献了资源，大奖实至名归{:1_124:} 个人信息无误，谢谢大赛管理员、组织者！

sunlin_future 发表于 2015-8-3 14:50 Xilinx SDAccel 软件多少钱

试用版本，不收费{:1_117:}

lan001 发表于 2015-6-8 00:42 请问怎样获取 Xilinx SDAccel 软件呢，我也想试用一下。请指点一下

找Avnet申请

guaiguaidou 发表于 2015-6-14 10:42 请问一下opencl怎么申请license？

找站内管理员申请即可

ZT_15 发表于 2015-6-5 16:18 博主您好！我是一名大四学生，专业是微电子，我的毕业设计是将CNN算法在FPGA上实现加速。前段时间忙于考研复试、调剂的事情，半个月以前才开始做毕设。通过查找各种资料，我对CNN算法思想已经掌握，并用Matlab语言实现了CNN算法，可以进行简单的图片识别。我了解到CNN算法在卷积层和全连接层运算量非常大，也是CNN算法在FPGA上实现加速需要重点考虑的地方，但是我是第一次接触OpenCL语言，将CNN卷积层和全连接层用OpenCL语言实现对我有很大难度。事关我能否毕业，我现在真的非常着急。今天我意外发现这个论坛，看到博主最近也在研究这个问题，感觉真是拨云见雾。博主好人，能不能将CNN算法的OpenCL全部实现代码发给我，我保证尊重博主的科研成果，不会发给别人。我知道我这样做非常不好，但是，我真的是没有办法了。我是新注册用户，不能跟博主私聊，如果博主看到了我的回复，请发发慈悲。我的邮箱是 。我会非常感激博主！

不好意思，目前还不能公开

qq365317289 发表于 2015-6-5 16:12 楼主好厉害~方便的话可以留个邮箱交流一下把~

已发私信

1696811157 发表于 2015-6-3 19:17 会不会是这个代码和de1不兼容呢？？？

64也不行。找Altera人问问吧。

1696811157 发表于 2015-6-3 10:52 是不是该FFT处理数据过多，改少了应该可以吧。。。突发奇想

我刚刚改成256点FFT，LE会爆，DSP够用。现在改成64点试试。不过，FFT短了没有意义呀，工程中常用的还是1024，2048点以上的

1696811157 发表于 2015-6-3 10:47 这板子可不是想换就换的。。。假如说资源用爆是电脑资源用爆还是DE1用爆

DE1板子资源很少的。报告显示DSP和LE资源都爆了。

找到原因了，资源用爆了，建议用其他板子试试。 ====================================================================================================================== |                                          *** Optimization Report ***                                               | | Warning: Compile with "-g" to get line number and variable name information                                        | ====================================================================================================================== | Kernel: fft1d                                                                                            | Ln.Col  | ====================================================================================================================== | Loop for.body                                                                                            |         | |     Pipelined execution inferred.                                                                        |         | ====================================================================================================================== +--------------------------------------------------------------------+ ; Estimated Resource Usage Summary                                   ; +----------------------------------------+---------------------------+ ; Resource                               + Usage                     ; +----------------------------------------+---------------------------+ ; Logic utilization                      ;  144%                     ; ; Dedicated logic registers              ;   64%                     ; ; Memory blocks                          ;   32%                     ; ; DSP blocks                             ;  107%                     ; +----------------------------------------+---------------------------; System name: fft1d Placing kernel fft1d at address 0x0 2015.06.03.09:21:34 Info: Doing: qsys-script --script=system.tcl --Xmx512M --XX:+UseSerialGC --system-file=system.qsys 2015.06.03.09:22:34 Info: set_validation_property AUTOMATIC_VALIDATION false 2015.06.03.09:22:34 Info: add_instance fft1d_system fft1d_system 2015.06.03.09:22:34 Info: add_connection acl_iface.kernel_clk fft1d_system.clock_reset 2015.06.03.09:22:34 Info: add_connection acl_iface.kernel_clk2x fft1d_system.clock_reset2x 2015.06.03.09:22:34 Info: add_connection acl_iface.kernel_reset fft1d_system.clock_reset_reset 2015.06.03.09:22:34 Info: add_connection fft1d_system.avm_memgmem0_port_0_0_rw acl_iface.kernel_mem0 2015.06.03.09:22:34 Info: add_connection acl_iface.kernel_irq fft1d_system.kernel_irq 2015.06.03.09:22:34 Info: add_instance cra_root cra_ring_root 2015.06.03.09:22:35 Info: set_instance_parameter_value cra_root DATA_W 64 2015.06.03.09:22:35 Info: set_instance_parameter_value cra_root ADDR_W 4 2015.06.03.09:22:35 Info: set_instance_parameter_value cra_root ID_W 0 2015.06.03.09:22:35 Info: add_connection acl_iface.kernel_clk cra_root.clock 2015.06.03.09:22:35 Info: add_connection acl_iface.kernel_reset cra_root.reset 2015.06.03.09:22:35 Info: add_connection acl_iface.kernel_cra cra_root.cra_slave 2015.06.03.09:22:35 Info: set_connection_parameter_value acl_iface.kernel_cra/cra_root.cra_slave baseAddress 0x0 2015.06.03.09:22:35 Info: add_instance avs_fft1d_cra_cra_ring cra_ring_node 2015.06.03.09:22:35 Info: set_instance_parameter_value avs_fft1d_cra_cra_ring DATA_W 64 2015.06.03.09:22:35 Info: set_instance_parameter_value avs_fft1d_cra_cra_ring RING_ADDR_W 4 2015.06.03.09:22:35 Info: set_instance_parameter_value avs_fft1d_cra_cra_ring CRA_ADDR_W 4 2015.06.03.09:22:35 Info: set_instance_parameter_value avs_fft1d_cra_cra_ring ID_W 0 2015.06.03.09:22:35 Info: set_instance_parameter_value avs_fft1d_cra_cra_ring ID 0 2015.06.03.09:22:35 Info: add_connection acl_iface.kernel_clk avs_fft1d_cra_cra_ring.clock 2015.06.03.09:22:35 Info: add_connection acl_iface.kernel_reset avs_fft1d_cra_cra_ring.reset 2015.06.03.09:22:35 Info: add_connection cra_root.ring_out avs_fft1d_cra_cra_ring.ring_in 2015.06.03.09:22:35 Info: add_connection avs_fft1d_cra_cra_ring.cra_master fft1d_system.avs_fft1d_cra 2015.06.03.09:22:35 Info: set_connection_parameter_value avs_fft1d_cra_cra_ring.cra_master/fft1d_system.avs_fft1d_cra baseAddress 0x0 2015.06.03.09:22:35 Info: add_connection avs_fft1d_cra_cra_ring.ring_out cra_root.ring_in 2015.06.03.09:22:35 Info: save_system 2015.06.03.09:22:38 Progress: Loading fft1d/system.qsys 2015.06.03.09:22:38 Progress: Reading input file 2015.06.03.09:22:39 Progress: Adding ext_clk_50 [clock_source 14.0] 2015.06.03.09:22:39 Progress: Parameterizing module ext_clk_50 2015.06.03.09:22:39 Progress: Adding acl_iface [acl_iface_system 1.0] 2015.06.03.09:23:10 Progress: Parameterizing module acl_iface 2015.06.03.09:23:10 Progress: Adding fft1d_system [fft1d_system 1.0] 2015.06.03.09:23:10 Progress: Parameterizing module fft1d_system 2015.06.03.09:23:10 Progress: Adding cra_root [cra_ring_root 1.0] 2015.06.03.09:23:10 Progress: Parameterizing module cra_root 2015.06.03.09:23:10 Progress: Adding avs_fft1d_cra_cra_ring [cra_ring_node 1.0] 2015.06.03.09:23:10 Progress: Parameterizing module avs_fft1d_cra_cra_ring 2015.06.03.09:23:10 Progress: Building connections 2015.06.03.09:23:10 Progress: Parameterizing connections 2015.06.03.09:23:10 Progress: Validating 2015.06.03.09:23:12 Progress: Done reading input file 2015.06.03.09:23:20 Info: system.acl_iface.acl_iface: There are recommended upgrades for: pll 2015.06.03.09:23:20 Info: system.acl_iface.acl_kernel_clk.acl_kernel_clk: There are recommended upgrades for: kernel_pll 2015.06.03.09:23:20 Info: system.acl_iface.acl_kernel_clk.kernel_pll: The legal reference clock frequency is 50.0 MHz..800.0 MHz 2015.06.03.09:23:20 Info: system.acl_iface.acl_kernel_clk.kernel_pll: Able to implement PLL with user settings 2015.06.03.09:23:20 Warning: system.acl_iface.acl_kernel_clk.acl_pll_reconfig: set_interface_assignment: Interface "mgmt_waitrequest" does not exist 2015.06.03.09:23:20 Warning: system.acl_iface.acl_kernel_clk.global_routing_kernel_clk.global_clk/kernel_clk.clk_in: kernel_clk.clk_in requires 100000000Hz, but source has frequency of 0Hz 2015.06.03.09:23:20 Warning: system.acl_iface.hps: "Configuration/HPS-to-FPGA user 0 clock frequency" (desired_cfg_clk_mhz) requested 100.0 MHz, but only achieved 97.368421 MHz 2015.06.03.09:23:20 Warning: system.acl_iface.hps: 1 or more output clock frequencies cannot be achieved precisely, consider revising desired output clock frequencies. 2015.06.03.09:23:20 Info: system.acl_iface.pll: The legal reference clock frequency is 5.0 MHz..800.0 MHz 2015.06.03.09:23:20 Info: system.acl_iface.pll: Able to implement PLL with user settings 2015.06.03.09:23:20 Warning: system.acl_iface: acl_iface.acl_kernel_clk_kernel_pll_locked must be exported, or connected to a matching conduit. 2015.06.03.09:23:20 Warning: system.acl_iface: acl_iface.acl_internal_memorg_kernel must be exported, or connected to a matching conduit. 2015.06.03.09:23:20 Warning: system.acl_iface: acl_iface.kernel_interface_acl_bsp_memorg_host must be exported, or connected to a matching conduit. 2015.06.03.09:23:20 Info: system: Generating system "system" for QUARTUS_SYNTH 2015.06.03.09:23:27 Info: Interconnect is inserted between master acl_iface.kernel_cra and slave cra_root.cra_slave because the master has burstcount signal 1 bit wide, but the slave is 0 bit wide. 2015.06.03.09:23:27 Info: Interconnect is inserted between master acl_iface.kernel_cra and slave cra_root.cra_slave because the master has address signal 30 bit wide, but the slave is 4 bit wide. 2015.06.03.09:23:27 Info: Interconnect is inserted between master acl_iface.kernel_cra and slave cra_root.cra_slave because the master has debugaccess signal 1 bit wide, but the slave is 0 bit wide. 2015.06.03.09:23:40 Info: Interconnect is inserted between master clock_cross_kernel_mem1.m0 and slave address_span_extender_kernel.windowed_slave because the master has address signal 30 bit wide, but the slave is 25 bit wide. 2015.06.03.09:23:40 Info: Interconnect is inserted between master clock_cross_kernel_mem1.m0 and slave address_span_extender_kernel.windowed_slave because the master has debugaccess signal 1 bit wide, but the slave is 0 bit wide. 2015.06.03.09:23:40 Info: Interconnect is inserted between master address_span_extender_kernel.expanded_master and slave hps.f2h_sdram0_data because the master has address signal 32 bit wide, but the slave is 27 bit wide. 2015.06.03.09:23:40 Info: Interconnect is inserted between master address_span_extender_kernel.expanded_master and slave hps.f2h_sdram0_data because the master has burstcount signal 5 bit wide, but the slave is 8 bit wide. 2015.06.03.09:23:41 Warning: hps.f2h_irq0: Cannot connect clock for irq_mapper.sender 2015.06.03.09:23:41 Warning: hps.f2h_irq0: Cannot connect reset for irq_mapper.sender 2015.06.03.09:23:41 Warning: hps.f2h_irq1: Cannot connect clock for irq_mapper_001.sender 2015.06.03.09:23:41 Warning: hps.f2h_irq1: Cannot connect reset for irq_mapper_001.sender 2015.06.03.09:23:48 Info: acl_iface: "system" instantiated acl_iface_system "acl_iface" 2015.06.03.09:23:48 Info: fft1d_system: "system" instantiated fft1d_system "fft1d_system" 2015.06.03.09:23:49 Info: cra_root: "system" instantiated cra_ring_root "cra_root" 2015.06.03.09:23:49 Info: avs_fft1d_cra_cra_ring: "system" instantiated cra_ring_node "avs_fft1d_cra_cra_ring" 2015.06.03.09:23:49 Info: mm_interconnect_0: "system" instantiated altera_mm_interconnect "mm_interconnect_0" 2015.06.03.09:23:50 Info: mm_interconnect_1: "system" instantiated altera_mm_interconnect "mm_interconnect_1" 2015.06.03.09:23:50 Info: irq_mapper: "system" instantiated altera_irq_mapper "irq_mapper" 2015.06.03.09:23:51 Info: Inserting clock-crossing logic between cmd_demux.src2 and cmd_mux_002.sink0 2015.06.03.09:23:51 Info: Inserting clock-crossing logic between rsp_demux_002.src0 and rsp_mux.sink2 2015.06.03.09:23:53 Info: acl_kernel_clk: "acl_iface" instantiated acl_kernel_clk "acl_kernel_clk" 2015.06.03.09:23:53 Info: clock_cross_kernel_mem1: "acl_iface" instantiated altera_avalon_mm_clock_crossing_bridge "clock_cross_kernel_mem1" 2015.06.03.09:23:53 Info: version_id: "acl_iface" instantiated version_id "version_id" 2015.06.03.09:23:53 Info: hps: "Running  for module: hps" 2015.06.03.09:23:54 Warning: hps: "Configuration/HPS-to-FPGA user 0 clock frequency" (desired_cfg_clk_mhz) requested 100.0 MHz, but only achieved 97.368421 MHz 2015.06.03.09:23:54 Warning: hps: 1 or more output clock frequencies cannot be achieved precisely, consider revising desired output clock frequencies. 2015.06.03.09:23:56 Info: hps: "acl_iface" instantiated altera_hps "hps" 2015.06.03.09:23:56 Info: Interconnect is inserted between master address_span_extender_0.expanded_master and slave kernel_cra.s0 because the master has readdata signal 32 bit wide, but the slave is 64 bit wide. 2015.06.03.09:23:56 Info: Interconnect is inserted between master address_span_extender_0.expanded_master and slave kernel_cra.s0 because the master has writedata signal 32 bit wide, but the slave is 64 bit wide. 2015.06.03.09:23:56 Info: Interconnect is inserted between master address_span_extender_0.expanded_master and slave kernel_cra.s0 because the master has byteenable signal 4 bit wide, but the slave is 8 bit wide. 2015.06.03.09:23:58 Info: Inserting clock-crossing logic between cmd_demux.src0 and cmd_mux.sink0 2015.06.03.09:23:58 Info: Inserting clock-crossing logic between cmd_demux.src1 and cmd_mux_001.sink0 2015.06.03.09:23:58 Info: Inserting clock-crossing logic between rsp_demux.src0 and rsp_mux.sink0 2015.06.03.09:23:58 Info: Inserting clock-crossing logic between rsp_demux_001.src0 and rsp_mux.sink1 2015.06.03.09:23:58 Warning: irq_ena_0.my_irq_in: Cannot connect clock for irq_mapper.sender 2015.06.03.09:23:58 Warning: irq_ena_0.my_irq_in: Cannot connect reset for irq_mapper.sender 2015.06.03.09:24:00 Info: acl_kernel_interface: "acl_iface" instantiated acl_kernel_interface "acl_kernel_interface" 2015.06.03.09:24:00 Info: pll: "acl_iface" instantiated altera_pll "pll" 2015.06.03.09:24:00 Info: address_span_extender_kernel: "acl_iface" instantiated altera_address_span_extender "address_span_extender_kernel" 2015.06.03.09:24:01 Info: mm_interconnect_0: "acl_iface" instantiated altera_mm_interconnect "mm_interconnect_0" 2015.06.03.09:24:01 Info: mm_interconnect_1: "acl_iface" instantiated altera_mm_interconnect "mm_interconnect_1" 2015.06.03.09:24:02 Info: mm_interconnect_2: "acl_iface" instantiated altera_mm_interconnect "mm_interconnect_2" 2015.06.03.09:24:02 Info: irq_mapper: "acl_iface" instantiated altera_irq_mapper "irq_mapper" 2015.06.03.09:24:02 Info: irq_mapper_001: "acl_iface" instantiated altera_irq_mapper "irq_mapper_001" 2015.06.03.09:24:02 Info: rst_controller: "acl_iface" instantiated altera_reset_controller "rst_controller" 2015.06.03.09:24:02 Info: fft1d_system_avm_memgmem0_port_0_0_rw_translator: "mm_interconnect_0" instantiated altera_merlin_master_translator "fft1d_system_avm_memgmem0_port_0_0_rw_translator" 2015.06.03.09:24:02 Info: acl_iface_kernel_mem0_translator: "mm_interconnect_0" instantiated altera_merlin_slave_translator "acl_iface_kernel_mem0_translator" 2015.06.03.09:24:02 Info: kernel_pll: "acl_kernel_clk" instantiated altera_pll "kernel_pll" 2015.06.03.09:24:10 Info: pll_reconfig_0: "acl_kernel_clk" instantiated acl_pll_reconfig "pll_reconfig_0" 2015.06.03.09:24:10 Info: pll_rom: Starting RTL generation for module 'system_acl_iface_acl_kernel_clk_pll_rom' 2015.06.03.09:24:10 Info: pll_rom:   Generation command is [exec G:/altera/quartus/bin64/perl/bin/perl.exe -I G:/altera/quartus/bin64/perl/lib -I G:/altera/quartus/sopc_builder/bin/europa -I G:/altera/quartus/sopc_builder/bin/perl_lib -I G:/altera/quartus/sopc_builder/bin -I G:/altera/quartus/../ip/altera/sopc_builder_ip/common -I G:/altera/quartus/../ip/altera/sopc_builder_ip/altera_avalon_onchip_memory2 -- G:/altera/quartus/../ip/altera/sopc_builder_ip/altera_avalon_onchip_memory2/generate_rtl.pl --name=system_acl_iface_acl_kernel_clk_pll_rom --dir=C:/Users/yongke.zyk/AppData/Local/Temp/alt6589_6403431607200015766.dir/0015_pll_rom_gen/ --quartus_dir=G:/altera/quartus --verilog --config=C:/Users/yongke.zyk/AppData/Local/Temp/alt6589_6403431607200015766.dir/0015_pll_rom_gen//system_acl_iface_acl_kernel_clk_pll_rom_component_configuration.pl  --do_build_sim=0  ] 2015.06.03.09:24:12 Info: pll_rom: Done RTL generation for module 'system_acl_iface_acl_kernel_clk_pll_rom' 2015.06.03.09:24:12 Info: pll_rom: "acl_kernel_clk" instantiated altera_avalon_onchip_memory2 "pll_rom" 2015.06.03.09:24:12 Info: counter: "acl_kernel_clk" instantiated timer "counter" 2015.06.03.09:24:12 Info: global_routing_kernel_clk: "acl_kernel_clk" instantiated global_routing_clk "global_routing_kernel_clk" 2015.06.03.09:24:12 Info: ctrl: "acl_kernel_clk" instantiated altera_avalon_mm_bridge "ctrl" 2015.06.03.09:24:12 Info: pll_sw_reset: "acl_kernel_clk" instantiated sw_reset "pll_sw_reset" 2015.06.03.09:24:12 Info: pll_lock_avs_0: "acl_kernel_clk" instantiated pll_lock_avs "pll_lock_avs_0" 2015.06.03.09:24:13 Info: mm_interconnect_0: "acl_kernel_clk" instantiated altera_mm_interconnect "mm_interconnect_0" 2015.06.03.09:24:13 Info: fpga_interfaces: "hps" instantiated altera_interface_generator "fpga_interfaces" 2015.06.03.09:24:14 Info: hps_io: "hps" instantiated altera_hps_io "hps_io" 2015.06.03.09:24:14 Info: sys_description_rom: Starting RTL generation for module 'system_acl_iface_acl_kernel_interface_sys_description_rom' 2015.06.03.09:24:14 Info: sys_description_rom:   Generation command is [exec G:/altera/quartus/bin64/perl/bin/perl.exe -I G:/altera/quartus/bin64/perl/lib -I G:/altera/quartus/sopc_builder/bin/europa -I G:/altera/quartus/sopc_builder/bin/perl_lib -I G:/altera/quartus/sopc_builder/bin -I G:/altera/quartus/../ip/altera/sopc_builder_ip/common -I G:/altera/quartus/../ip/altera/sopc_builder_ip/altera_avalon_onchip_memory2 -- G:/altera/quartus/../ip/altera/sopc_builder_ip/altera_avalon_onchip_memory2/generate_rtl.pl --name=system_acl_iface_acl_kernel_interface_sys_description_rom --dir=C:/Users/yongke.zyk/AppData/Local/Temp/alt6589_6403431607200015766.dir/0017_sys_description_rom_gen/ --quartus_dir=G:/altera/quartus --verilog --config=C:/Users/yongke.zyk/AppData/Local/Temp/alt6589_6403431607200015766.dir/0017_sys_description_rom_gen//system_acl_iface_acl_kernel_interface_sys_description_rom_component_configuration.pl  --do_build_sim=0  ] 2015.06.03.09:24:14 Info: sys_description_rom: Done RTL generation for module 'system_acl_iface_acl_kernel_interface_sys_description_rom' 2015.06.03.09:24:14 Info: sys_description_rom: "acl_kernel_interface" instantiated altera_avalon_onchip_memory2 "sys_description_rom" 2015.06.03.09:24:14 Info: mem_org_mode: "acl_kernel_interface" instantiated mem_org_mode "mem_org_mode" 2015.06.03.09:24:14 Info: irq_bridge_0: "acl_kernel_interface" instantiated altera_irq_bridge "irq_bridge_0" 2015.06.03.09:24:14 Info: irq_ena_0: "acl_kernel_interface" instantiated irq_ena "irq_ena_0" 2015.06.03.09:24:14 Info: mm_interconnect_0: "acl_kernel_interface" instantiated altera_mm_interconnect "mm_interconnect_0" 2015.06.03.09:24:16 Info: mm_interconnect_1: "acl_kernel_interface" instantiated altera_mm_interconnect "mm_interconnect_1" 2015.06.03.09:24:16 Info: hps_h2f_lw_axi_master_agent: "mm_interconnect_0" instantiated altera_merlin_axi_master_ni "hps_h2f_lw_axi_master_agent" 2015.06.03.09:24:16 Info: version_id_s_agent: "mm_interconnect_0" instantiated altera_merlin_slave_agent "version_id_s_agent" 2015.06.03.09:24:16 Info: version_id_s_agent_rsp_fifo: "mm_interconnect_0" instantiated altera_avalon_sc_fifo "version_id_s_agent_rsp_fifo" 2015.06.03.09:24:16 Info: router: "mm_interconnect_0" instantiated altera_merlin_router "router" 2015.06.03.09:24:16 Info: router_002: "mm_interconnect_0" instantiated altera_merlin_router "router_002" 2015.06.03.09:24:16 Info: hps_h2f_lw_axi_master_wr_limiter: "mm_interconnect_0" instantiated altera_merlin_traffic_limiter "hps_h2f_lw_axi_master_wr_limiter" 2015.06.03.09:24:16 Info: Reusing file C:/ATRP/fft1d/fft1d/fft1d/system/synthesis/submodules/altera_avalon_sc_fifo.v 2015.06.03.09:24:17 Info: version_id_s_burst_adapter: "mm_interconnect_0" instantiated altera_merlin_burst_adapter "version_id_s_burst_adapter" 2015.06.03.09:24:17 Info: Reusing file C:/ATRP/fft1d/fft1d/fft1d/system/synthesis/submodules/altera_merlin_address_alignment.sv 2015.06.03.09:24:17 Info: Reusing file C:/ATRP/fft1d/fft1d/fft1d/system/synthesis/submodules/altera_avalon_st_pipeline_base.v 2015.06.03.09:24:17 Info: cmd_demux: "mm_interconnect_0" instantiated altera_merlin_demultiplexer "cmd_demux" 2015.06.03.09:24:17 Info: cmd_mux: "mm_interconnect_0" instantiated altera_merlin_multiplexer "cmd_mux" 2015.06.03.09:24:17 Info: rsp_demux: "mm_interconnect_0" instantiated altera_merlin_demultiplexer "rsp_demux" 2015.06.03.09:24:17 Info: rsp_mux: "mm_interconnect_0" instantiated altera_merlin_multiplexer "rsp_mux" 2015.06.03.09:24:17 Info: Reusing file C:/ATRP/fft1d/fft1d/fft1d/system/synthesis/submodules/altera_merlin_arbitrator.sv 2015.06.03.09:24:17 Info: address_span_extender_kernel_expanded_master_agent: "mm_interconnect_2" instantiated altera_merlin_master_agent "address_span_extender_kernel_expanded_master_agent" 2015.06.03.09:24:17 Info: router: "mm_interconnect_2" instantiated altera_merlin_router "router" 2015.06.03.09:24:17 Info: router_001: "mm_interconnect_2" instantiated altera_merlin_router "router_001" 2015.06.03.09:24:17 Info: cmd_demux: "mm_interconnect_2" instantiated altera_merlin_demultiplexer "cmd_demux" 2015.06.03.09:24:17 Info: cmd_mux: "mm_interconnect_2" instantiated altera_merlin_multiplexer "cmd_mux" 2015.06.03.09:24:17 Info: Reusing file C:/ATRP/fft1d/fft1d/fft1d/system/synthesis/submodules/altera_merlin_arbitrator.sv 2015.06.03.09:24:17 Info: rsp_mux: "mm_interconnect_2" instantiated altera_merlin_multiplexer "rsp_mux" 2015.06.03.09:24:17 Info: Reusing file C:/ATRP/fft1d/fft1d/fft1d/system/synthesis/submodules/altera_merlin_arbitrator.sv 2015.06.03.09:24:17 Info: router: "mm_interconnect_0" instantiated altera_merlin_router "router" 2015.06.03.09:24:17 Info: router_001: "mm_interconnect_0" instantiated altera_merlin_router "router_001" 2015.06.03.09:24:17 Info: router_003: "mm_interconnect_0" instantiated altera_merlin_router "router_003" 2015.06.03.09:24:17 Info: cmd_demux: "mm_interconnect_0" instantiated altera_merlin_demultiplexer "cmd_demux" 2015.06.03.09:24:17 Info: cmd_mux: "mm_interconnect_0" instantiated altera_merlin_multiplexer "cmd_mux" 2015.06.03.09:24:17 Info: Reusing file C:/ATRP/fft1d/fft1d/fft1d/system/synthesis/submodules/altera_merlin_arbitrator.sv 2015.06.03.09:24:17 Info: cmd_mux_002: "mm_interconnect_0" instantiated altera_merlin_multiplexer "cmd_mux_002" 2015.06.03.09:24:17 Info: Reusing file C:/ATRP/fft1d/fft1d/fft1d/system/synthesis/submodules/altera_merlin_arbitrator.sv 2015.06.03.09:24:17 Info: rsp_demux: "mm_interconnect_0" instantiated altera_merlin_demultiplexer "rsp_demux" 2015.06.03.09:24:17 Info: rsp_demux_002: "mm_interconnect_0" instantiated altera_merlin_demultiplexer "rsp_demux_002" 2015.06.03.09:24:17 Info: rsp_mux: "mm_interconnect_0" instantiated altera_merlin_multiplexer "rsp_mux" 2015.06.03.09:24:17 Info: Reusing file C:/ATRP/fft1d/fft1d/fft1d/system/synthesis/submodules/altera_merlin_arbitrator.sv 2015.06.03.09:24:17 Info: crosser: "mm_interconnect_0" instantiated altera_avalon_st_handshake_clock_crosser "crosser" 2015.06.03.09:24:17 Info: Reusing file C:/ATRP/fft1d/fft1d/fft1d/system/synthesis/submodules/altera_avalon_st_pipeline_base.v 2015.06.03.09:24:44 Info: border: "hps_io" instantiated altera_interface_generator "border" 2015.06.03.09:24:44 Info: router: "mm_interconnect_0" instantiated altera_merlin_router "router" 2015.06.03.09:24:44 Info: router_001: "mm_interconnect_0" instantiated altera_merlin_router "router_001" 2015.06.03.09:24:44 Info: cmd_demux: "mm_interconnect_0" instantiated altera_merlin_demultiplexer "cmd_demux" 2015.06.03.09:24:44 Info: cmd_mux: "mm_interconnect_0" instantiated altera_merlin_multiplexer "cmd_mux" 2015.06.03.09:24:44 Info: Reusing file C:/ATRP/fft1d/fft1d/fft1d/system/synthesis/submodules/altera_merlin_arbitrator.sv 2015.06.03.09:24:44 Info: rsp_mux: "mm_interconnect_0" instantiated altera_merlin_multiplexer "rsp_mux" 2015.06.03.09:24:44 Info: Reusing file C:/ATRP/fft1d/fft1d/fft1d/system/synthesis/submodules/altera_merlin_arbitrator.sv 2015.06.03.09:24:44 Info: kernel_cra_s0_cmd_width_adapter: "mm_interconnect_0" instantiated altera_merlin_width_adapter "kernel_cra_s0_cmd_width_adapter" 2015.06.03.09:24:44 Info: Reusing file C:/ATRP/fft1d/fft1d/fft1d/system/synthesis/submodules/altera_merlin_address_alignment.sv 2015.06.03.09:24:44 Info: Reusing file C:/ATRP/fft1d/fft1d/fft1d/system/synthesis/submodules/altera_merlin_burst_uncompressor.sv 2015.06.03.09:24:44 Info: router: "mm_interconnect_1" instantiated altera_merlin_router "router" 2015.06.03.09:24:44 Info: router_001: "mm_interconnect_1" instantiated altera_merlin_router "router_001" 2015.06.03.09:24:44 Info: router_002: "mm_interconnect_1" instantiated altera_merlin_router "router_002" 2015.06.03.09:24:44 Info: router_003: "mm_interconnect_1" instantiated altera_merlin_router "router_003" 2015.06.03.09:24:44 Info: router_005: "mm_interconnect_1" instantiated altera_merlin_router "router_005" 2015.06.03.09:24:44 Info: cmd_demux: "mm_interconnect_1" instantiated altera_merlin_demultiplexer "cmd_demux" 2015.06.03.09:24:44 Info: cmd_mux: "mm_interconnect_1" instantiated altera_merlin_multiplexer "cmd_mux" 2015.06.03.09:24:44 Info: Reusing file C:/ATRP/fft1d/fft1d/fft1d/system/synthesis/submodules/altera_merlin_arbitrator.sv 2015.06.03.09:24:44 Info: cmd_mux_002: "mm_interconnect_1" instantiated altera_merlin_multiplexer "cmd_mux_002" 2015.06.03.09:24:44 Info: Reusing file C:/ATRP/fft1d/fft1d/fft1d/system/synthesis/submodules/altera_merlin_arbitrator.sv 2015.06.03.09:24:44 Info: rsp_demux: "mm_interconnect_1" instantiated altera_merlin_demultiplexer "rsp_demux" 2015.06.03.09:24:44 Info: rsp_demux_002: "mm_interconnect_1" instantiated altera_merlin_demultiplexer "rsp_demux_002" 2015.06.03.09:24:44 Info: rsp_mux: "mm_interconnect_1" instantiated altera_merlin_multiplexer "rsp_mux" 2015.06.03.09:24:44 Info: Reusing file C:/ATRP/fft1d/fft1d/fft1d/system/synthesis/submodules/altera_merlin_arbitrator.sv 2015.06.03.09:24:44 Info: system: Done "system" with 85 modules, 199 files 复制代码

1696811157 发表于 2015-6-2 15:24 https://www.altera.com.cn/support/support-resources/design-examples/design-software/opencl/opencl.html 其中FFT1d的例子，所用软件是14.0.谢谢

正在编译，等等看会不会出现你说的情形

chenzhufly 发表于 2015-6-1 21:26 这个alex不是开坛授课了吗 我也在努力的学习中呢

原来已经发了，还没看

Show me the code please