我是在看pm电源管理的mdd层代码的时候发现的，pmimpl.h,pmstream.cpp
// this structure describes a power-manageable device
typedef struct _DeviceState_tag {
LPCTSTR pszName; // device's name
CEDEVICE_POWER_STATE curDx; // current official power state (not necessarily supported by the device)
CEDEVICE_POWER_STATE floorDx; // minimum device power state, or PwrDeviceUnspecified
CEDEVICE_POWER_STATE ceilingDx; // maximum device power state, or PwrDeviceUnspecified
CEDEVICE_POWER_STATE setDx; // power state if explicitly set, or PwrDeviceUnspecified
CEDEVICE_POWER_STATE lastReqDx; // last state requested by the device
CEDEVICE_POWER_STATE actualDx; // current actual device power state
CEDEVICE_POWER_STATE pendingDx; // Pending DX for updating
DWORD dwNumPending; // Number of Pending for updating.
struct _DeviceState_tag *pParent; // parent device, or NULL POWER_CAPABILITIES caps; // as reported by the device
DWORD dwRefCount; // structure can be deallocated when this is 0
HANDLE hDevice; // handle to the device from OpenDevice(), or NULL
PDEVICE_INTERFACE pInterface; // interface to the device class power management routines
struct _DeviceList_tag *pListHead; // pointer to the containing list
struct _DeviceState_tag *pNext; // linked list pointers
struct _DeviceState_tag *pPrev;
} DEVICE_STATE, *PDEVICE_STATE;
static HANDLE
OpenStreamDevice(PDEVICE_STATE pds)
{
PDEVICE_STATE pdsReal = pds;
SETFNAME(_T("OpenStreamDevice"));
// determine what device to actually open
if(pds->pParent != NULL) {
pdsReal = pds->pParent;
}
// get a handle to the client
HANDLE hRet = CreateFile(pdsReal->pszName, 0,
FILE_SHARE_READ|FILE_SHARE_WRITE, NULL, OPEN_EXISTING, 0, NULL);
if(hRet == INVALID_HANDLE_VALUE) {
PMLOGMSG(ZONE_WARN || ZONE_IOCTL, (_T("%s: OpenFile('%s') failed %d (0x%08x)\r\n"), pszFname,
pdsReal->pszName, GetLastError(), GetLastError()));
}
PMLOGMSG(ZONE_DEVICE || ZONE_IOCTL, (_T("%s: handle to '%s' on behalf of '%s' is 0x%08x\r\n"), \
pszFname, pdsReal->pszName, pds->pszName, hRet));
return hRet;
}
打开一个流接口设备的时候，获取的是他的父设备的句柄，我开始我有点奇怪，后来发现，在添加设备的时候，那个parent的参数是NULL的，也就是wince6.0中还没有用到，留着以后用。具体这也都是我的猜测。
去掉MMU的话，不行，程序都跑得不对了，我用syslib.c中的相同映像表，放在我demo板上一个工程里面跑，VxWorks镜像启动后，是可以访问d 0xf0040000的,映像表如下：
UINT32 sysBatDesc [2 * (_MMU_NUM_IBAT + _MMU_NUM_DBAT)] =
{
/* I BAT 0 */
((0xf8000000 & _MMU_UBAT_BEPI_MASK) | _MMU_UBAT_BL_32M |
_MMU_UBAT_VS | _MMU_UBAT_VP),
((0xf8000000 & _MMU_LBAT_BRPN_MASK) | _MMU_LBAT_PP_RW |
_MMU_LBAT_CACHE_INHIBIT),
/*0, 0,*/
/* I BAT 1 */
0, 0,
/* I BAT 2 */
0, 0,
/* I BAT 3 */
0, 0,
/* D BAT 0 */
((0xf8000000 & _MMU_UBAT_BEPI_MASK) | _MMU_UBAT_BL_32M |
_MMU_UBAT_VS | _MMU_UBAT_VP),
((0xf8000000 & _MMU_LBAT_BRPN_MASK) | _MMU_LBAT_PP_RW |
_MMU_LBAT_CACHE_INHIBIT),
/*0, 0,*/
/* D BAT 1 */
/* use DBAT1 to map CPM DPRAM and internal registers into data space */
/* NOTE! the internal space cannot be cached and should be guarded */
((0xF0000000 & _MMU_UBAT_BEPI_MASK) | _MMU_UBAT_BL_128K |
_MMU_UBAT_VS | _MMU_UBAT_VP),
((0xF0000000 & _MMU_LBAT_BRPN_MASK) | _MMU_LBAT_PP_RW |
_MMU_LBAT_CACHE_INHIBIT | _MMU_LBAT_GUARDED),
/* D BAT 2 */
0,0,
/* D BAT 3 */
0,0
};
/*
* sysPhysMemDesc[] is used to initialize the Page Table Entry (PTE) array
* used by the MMU to translate addresses with single page (4k) granularity.
* PTE memory space should not, in general, overlap BAT memory space but
* may be allowed if only Data or Instruction access is mapped via BAT.
*
* Address translations for local RAM, memory mapped PCI bus, the Board Control and
* Status registers, the MPC8260 Internal Memory Map, and local FLASH RAM are set here.
*
* PTEs are held, strangely enough, in a Page Table. Page Table sizes are
* integer powers of two based on amount of memory to be mapped and a
* minimum size of 64 kbytes. The MINIMUM recommended Page Table sizes
* for 32-bit PowerPCs are:
*
* Total mapped memory Page Table size
* ------------------- ---------------
* 8 Meg 64 K
* 16 Meg 128 K
* 32 Meg 256 K
* 64 Meg 512 K
* 128 Meg 1 Meg
* . .
* . .
* . .
*
* [Ref: chapter 7, PowerPC Microprocessor Family: The Programming Environments]
*
*/
PHYS_MEM_DESC sysPhysMemDesc [] =
{
{
/* Vector Table and Interrupt Stack */
(void *) 0x00000000,
(void *) 0x00000000,
0x00010000,
VM_STATE_MASK_VALID | VM_STATE_MASK_WRITABLE | VM_STATE_MASK_CACHEABLE,
VM_STATE_VALID | VM_STATE_WRITABLE | VM_STATE_CACHEABLE_NOT
},
{
/* RAM on 60x bus - Must be second entry for Auto Sizing */
(void *) 0x00010000,
(void *) 0x00010000,
0x08000000 - 0x00010000,
VM_STATE_MASK_VALID | VM_STATE_MASK_WRITABLE |
VM_STATE_MASK_CACHEABLE | VM_STATE_MASK_MEM_COHERENCY,
VM_STATE_VALID | VM_STATE_WRITABLE |
VM_STATE_CACHEABLE | VM_STATE_MEM_COHERENCY
},
{
/* MPC8260 Internal Memory Map */
(void *) 0xf000000,/*0xf000000*/
(void *) 0xf000000,
0x20000,/*0x20000*/
VM_STATE_MASK_VALID | VM_STATE_MASK_WRITABLE | VM_STATE_MASK_CACHEABLE |
VM_STATE_MASK_GUARDED,
VM_STATE_VALID | VM_STATE_WRITABLE | VM_STATE_CACHEABLE_NOT |
VM_STATE_GUARDED
},
{
/* MPC8272 HPI Memory Map */
(void *) 0x0d000000,/*0x0d000000*/
(void *) 0x0d000000,
0x100000,/*0x100000*/
VM_STATE_MASK_VALID | VM_STATE_MASK_WRITABLE | VM_STATE_MASK_CACHEABLE |
VM_STATE_MASK_GUARDED,
VM_STATE_VALID | VM_STATE_WRITABLE | VM_STATE_CACHEABLE_NOT |
VM_STATE_GUARDED
},
{
/* MPC8272 fpga0 Memory Map */
(void *) 0x0e000000,/*0x0e000000*/
(void *) 0x0e000000,
0x40000,/*0x40000*/
VM_STATE_MASK_VALID | VM_STATE_MASK_WRITABLE | VM_STATE_MASK_CACHEABLE |
VM_STATE_MASK_GUARDED,
VM_STATE_VALID | VM_STATE_WRITABLE | VM_STATE_CACHEABLE_NOT |
VM_STATE_GUARDED
},
#if 1
{
/* MPC8272 fpga1 Memory Map */
(void *) 0x0f000000,/*0x0f000000*/
(void *) 0x0f000000,
0x100000,/*0x100000*/
VM_STATE_MASK_VALID | VM_STATE_MASK_WRITABLE | VM_STATE_MASK_CACHEABLE |
VM_STATE_MASK_GUARDED,
VM_STATE_VALID | VM_STATE_WRITABLE | VM_STATE_CACHEABLE_NOT |
VM_STATE_GUARDED
},
#endif
{
/* MPC8272 coder Memory Map */
(void *) 0x0A000000,/*0x0A000000*/
(void *) 0x0A000000,
0x100000,/*0x100000*/
VM_STATE_MASK_VALID | VM_STATE_MASK_WRITABLE | VM_STATE_MASK_CACHEABLE |
VM_STATE_MASK_GUARDED,
VM_STATE_VALID | VM_STATE_WRITABLE | VM_STATE_CACHEABLE_NOT |
VM_STATE_GUARDED
},
{
/* MPC8272 decoder Memory Map */
(void *) 0x0c000000,/*0x0c000000*/
(void *) 0x0c000000,
0x100000,/*0x100000*/
VM_STATE_MASK_VALID | VM_STATE_MASK_WRITABLE | VM_STATE_MASK_CACHEABLE |
VM_STATE_MASK_GUARDED,
VM_STATE_VALID | VM_STATE_WRITABLE | VM_STATE_CACHEABLE_NOT |
VM_STATE_GUARDED
},
#ifdef INCLUDE_PCI
{
(void*)0x80000000,/*0x80000000*/
(void*)0x80000000,
0x01000000,/*0x01000000*/
VM_STATE_MASK_VALID | VM_STATE_MASK_WRITABLE | VM_STATE_MASK_CACHEABLE |
VM_STATE_MASK_GUARDED,
VM_STATE_VALID | VM_STATE_WRITABLE | VM_STATE_CACHEABLE_NOT |
VM_STATE_GUARDED
},
{
(void*)0x90000000,/*0x90000000*/
(void*)0x90000000,
0x01000000,/*0x01000000*/
VM_STATE_MASK_VALID | VM_STATE_MASK_WRITABLE | VM_STATE_MASK_CACHEABLE |
VM_STATE_MASK_GUARDED,
VM_STATE_VALID | VM_STATE_WRITABLE | VM_STATE_CACHEABLE_NOT |
VM_STATE_GUARDED
},
{
(void*)0xa0000000,/*0xa0000000*/
(void*)0xa0000000,
0x00100000,/*0x00100000*/
VM_STATE_MASK_VALID | VM_STATE_MASK_WRITABLE | VM_STATE_MASK_CACHEABLE |
VM_STATE_MASK_GUARDED,
VM_STATE_VALID | VM_STATE_WRITABLE | VM_STATE_CACHEABLE_NOT |
VM_STATE_GUARDED
},
{
/* MPC8266 PCI Interrupt Controller */
(void *) 0x4730000,/* 0x4730000*/
(void *) 0x4730000,
0x10000,/*0x10000*/
VM_STATE_MASK_VALID | VM_STATE_MASK_WRITABLE | VM_STATE_MASK_CACHEABLE |
VM_STATE_MASK_GUARDED,
VM_STATE_VALID | VM_STATE_WRITABLE | VM_STATE_CACHEABLE_NOT |
VM_STATE_GUARDED
},
{
/* MPC8260 Internal Memory Map */
(void *) 0x4800000, /*0x4800000*/
(void *) 0x4800000,
0x10000,/*0x10000*/
VM_STATE_MASK_VALID | VM_STATE_MASK_WRITABLE | VM_STATE_MASK_CACHEABLE |
VM_STATE_MASK_GUARDED,
VM_STATE_VALID | VM_STATE_WRITABLE | VM_STATE_CACHEABLE_NOT |
VM_STATE_GUARDED
},
#endif
#ifdef INCLUDE_SECURITY_ENGINE
{
(void *) 0xf0040000,/*0xf0040000*/
(void *) 0xf0040000,
0x20000,/*0x20000*/
VM_STATE_MASK_VALID | VM_STATE_MASK_WRITABLE | VM_STATE_MASK_CACHEABLE |
VM_STATE_MASK_GUARDED,
VM_STATE_VALID | VM_STATE_WRITABLE | VM_STATE_CACHEABLE_NOT |
VM_STATE_GUARDED
},
#endif INCLUDE_SECURITY_ENGINE
#if 1 /*CTDB_MPC8280*/
{
/* BIOS */
(void *) 0xfff00000,/*0xfff00000*/
(void *) 0xfff00000,
0x100000,/*0x100000*/
VM_STATE_MASK_VALID | VM_STATE_MASK_WRITABLE | VM_STATE_MASK_CACHEABLE |
VM_STATE_MASK_GUARDED,
VM_STATE_VALID | VM_STATE_WRITABLE | VM_STATE_CACHEABLE_NOT |
VM_STATE_GUARDED
},
{
/* Flash */
(void *) 0xf8000000,/*0xf8000000 */
(void *) 0xf8000000,
0x4000000,/*0x4000000*/
VM_STATE_MASK_VALID | VM_STATE_MASK_WRITABLE | VM_STATE_MASK_CACHEABLE |
VM_STATE_MASK_GUARDED,
VM_STATE_VALID | VM_STATE_WRITABLE | VM_STATE_CACHEABLE_NOT |
VM_STATE_GUARDED
},
#endif
};
DSP 与 ARM 处理器