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    1. Inductance Analysis of Chip scale package

      标签：PCB SI

      Simple analysis to estimate lead inductance requirements ? Example of extracting lead inductances in a Tessera mBGA ? Analysis of max operating clock frequency if limited by core switching

      下载次数 2次 资源类型 应用文档 上传时间 2013-11-14

    2. Simultaneous Switch Noise and Power Plane Bounce for CMOS

      标签：SI SSN

      The simultaneous switch noise (SSN) problem has traditionally been thought of as an inductance problem. When many silicon drivers on a silicon chip switch at the same time, current crowds into the chip Gnd inductance or the Chip Vdd inductance. Ground bounce occurs that is proportional to the inductance in the ground or Vdd lead and the rate of change of current: V=L*di/dt. This line of thinking has been effective at solving SSN problems for traditional lead frame packages. Inductance matrices that account for the mutual inductance between signal, power and Gnd conductors are combined with silicon driver models in a circuit simulator to produce the expected noise waveforms for an SSN event

      下载次数 0次 资源类型 应用文档 上传时间 2013-11-14

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