module TEST_DPRAM(clk,outA);
input clk;
output wire [7:0] outA;
wire [7:0] dpraminaddr;
wire [7:0] dpramindata;
wire [7:0] ramoutdataA;
wire WrEn;
// wire clken;
// assign clken = ~clk;
assign WrEn = (count == 3) ? clk : 0;
assign dpraminaddr = addrin;
assign dpramindata = datain;
assign outA = ramoutdataA;
integer count = 0;
always @(posedge clk)
begin
if(count == 3)
begin
count