夏老师:您好!
请问我想要用verilog定义一个类似于下面C语言定义的数组的功能快,应该怎么定义呢?我在很多资料上看到都说verilog不支持数组?
unsigned char code GC0[]={0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00};//GC0
unsigned char code GC1[]={0x00,0x00,0x06,0x09,0x02,0x06,0x16,0x00};//GC1
unsigned char code GC2[]={0x11,0x11,0x11,0x11,0x11,0x11,0x11,0x11};//GC2
unsigned char code GC3[]={0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00};//GC3