一个简单的VHDL实现,可以对地址0x0709译码,并写入一个字节 library ieee; use ieee.std_logic_1164.all; entity test is     port (         addr: in std_logic_vector(15 downto 0);         data: in integer range 0 to 255;         nwr:  in std_logic;         nrd:  in std_logic;         ncs:  in std_logic); end entity test; architecture a1 of test is     signal work_reg:    integer range 0 to 255;     signal n_reg_write: std_logic; begin     n_reg_write