/*
SPI_Master_test
Its main purpose is to showing the SPI translation.
IO illuminate
BASIC_CLK:CPLD's clk(in this example use 22.0980Mhz);
SDI :Serial Data input(in this example we not use)
SDO :Serial Data output
SCK :SPI clk
CS :Chip Select
Enable :Enable the translation
*/
module SPI_Master_test (Enable,BASIC_CLK,SDI,SDO,SCK,CS);
output SDO,SCK,CS;
input BASIC_CLK,SDI,Enable;
reg SCK,SDO;
reg CS='b0;
reg Begin_Flag='b0;
reg [7:0] SPI_CLK_counter='b00000000;
reg [3:0] SD_8Bit_Counter='b0000;
reg [7:0] Serial_Data='b00000000;
initial
begin
Serial_Data='b11111000;
end
/*
CLK generator
*/
always @(posedge BASIC_CLK)
begin
SPI_CLK_counter<=SPI_CLK_counter+1;
case(SPI_CLK_counter)
'd11: SCK<=1;
'd22: begin
SCK<=0;
SPI_CLK_counter<=0;
end
endcase
end
/*
eight bit counter and set begin flag
*/
always @(posedge SCK)
begin
if(Enable)
begin
if(SD_8Bit_Counter=='d8)
begin
SD_8Bit_Counter<=0;
Begin_Flag<=1;
end
else
SD_8Bit_Counter<=SD_8Bit_Counter+1;
end
else
begin
SD_8Bit_Counter<=0;
Begin_Flag<=0;
end
end
/*
SET CS
*/
always @(posedge SCK)
begin
if(Enable)
begin
case(SD_8Bit_Counter)
'b1000:
CS<=1;
default:
CS<=0;
endcase
end
else
CS<=0;
end
/*
when negative comes prepairing the data for the positive
*/
always @(negedge SCK)
begin
if(Begin_Flag==1)
begin
case(SD_8Bit_Counter)
'b0000:
SDO<=Serial_Data[7];
'b0001:
SDO<=Serial_Data[6];
'b0010:
SDO<=Serial_Data[5];
'b0011:
SDO<=Serial_Data[4];
'b0100:
SDO<=Serial_Data[3];
'b0101:
SDO<=Serial_Data[2];
'b0110:
SDO<=Serial_Data[1];
'b0111:
SDO<=Serial_Data[0];
default:
SDO<=0;
endcase
end
end
endmodule