请完成以下验证码
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module dyn_seg(
input clk ,//clk_200hz
input reset_l ,
input [13:0] data ,
output reg [3:0] seg_s ,//用于片选的寄存器
output reg [7:0] seg //用于段选的寄存器
);
// *************************
// SIGNALS
// *************************
reg [1:0] cnt_show ;
wire [3:0] data0 ;// 定义四个功能寄存器
wire [3:0] data1 ;
wire [3:0] data2 ;
wire [3:0] data3 ;
reg [3:0] hex ;
// *************************
// CODE
// *************************
assign data0 = data/1000;最高位
assign data1 = data%1000/100;次位
assign data2 = data%100/10;倒数第二位
assign data3 = data%10;最低位
always @ (negedge reset_l or posedge clk)
begin
if (!reset_l) begin
cnt_show <= 2'b0;
end
else begin
cnt_show <= cnt_show+2'b1;
end
end
always @ (negedge reset_l or posedge clk)
begin
if(!reset_l) begin
seg_s <= 4'b0;
end
else begin
case(cnt_show[1:0])
2'b00 : seg_s <= 4'b0001;
2'b01 : seg_s <= 4'b0010;
2'b10 : seg_s <= 4'b0100;
2'b11 : seg_s <= 4'b1000;
default: ;
endcase
end
end
always @ (*)
begin
|
00 |
01 |
10 |
11 |
case(cnt_show[1:0])
2'b00 : hex <= data0;
2'b01 : hex <= data1;
2'b10 : hex <= data2;
2'b11 : hex <= data3;
default:hex <= 4'b0;
endcase
end
always @ (negedge reset_l or posedge clk)
begin
if (!reset_l) begin
seg <= 8'b0;
end
else begin
case(hex)
4'h0: seg <= 8'b11000000;
4'h1: seg <= 8'b11111001;
4'h2: seg <= 8'b10100100;
4'h3: seg <= 8'b10110000;
4'h4: seg <= 8'b10011001;
4'h5: seg <= 8'b10010010;
4'h6: seg <= 8'b10000010;
4'h7: seg <= 8'b11111000;
4'h8: seg <= 8'b10000000;
4'h9: seg <= 8'b10010000;
4'hA: seg <= 8'b01110111;
4'hB: seg <= 8'b01111100;
4'hC: seg <= 8'b00111001;
4'hD: seg <= 8'b01011110;
4'hE: seg <= 8'b01111001;
4'hF: seg <= 8'b01110001;
default: ;
endcase
end
end
//// *************************
//// SUBMODULE
//// *************************
Endmodule
大家看到我用singaltap抓到的波形有时钟 计数器 片选寄存器 段选寄存器
每个寄存器的波形以及在某一段的区间内 的关系
|
2813 |
从图上我们可以看到我抓到的波形例如2813
|
10100100 |
10000000 |
11111001 |
10110000 |
|
00 |
01 |
10 |
11 |