vhdl 4*4矩阵键盘程序

library ieee;

use ieee.std_logic_1164.all;

use ieee.std_logic_unsigned.all;

entity key44 is

generic(width: positive :=4);

port(clk :in std_logic;

column : in std_logic_vector(3 downto 0);

row : out std_logic_vector(3 downto 0);

num : out integer range 0 to 15 );

end entity;

architecture beha of key44 is

component key is

port(clk :in std_logic;

din : in std_logic;

dout : out std_logic);

end component;

signal count: std_logic_vector(1 downto 0);

signal row_v,column_v: std_logic_vector(3 downto 0);

signal z : std_logic_vector(5 downto 0);

begin

u1:for i in 0 to width-1 generate

U1: key port map (clk,column(i),column_v(i)); --去抖

end generate;--产生扫描信号

process(clk)

begin

if(rising_edge(clk))then

if(count="11")then

count<="00";

else

count<=count+'1';

end if;

end if;

end process;

row_v <= "1110" when count="00" else

"1101" when count="01" else

"1011" when count="10" else

"0111" ;

row<=row_v;

z<=count&column;

process(clk,z)--译码

begin

if(rising_edge(clk))then

case z is

when "001110" => num<=0;

when "001101" => num<=1;

when "001011" => num<=2;

when "000111" => num<=3;

when "011110" => num<=4;

when "011101" => num<=5;

when "011011" => num<=6;

when "010111" => num<=7;

when "101110" => num<=8;

when "101101" => num<=9;

when "101011" => num<=10;

when "100111" => num<=11;

when "111110" => num<=12;

when "111101" => num<=13;

when "111011" => num<=14;

when "110111" => num<=15;

when others => null;

end case;

end if;

end process;

end architecture;