笔记之Flash Memory

1.    Flash Memory Segmentaton:

Segment ,mian segment ,information segment

2.    Flash Memory Timing Generator

3.    Erasing Flash Memory

4.    Initiating an Erase from Within Flash Memory:

When a flash segment erase operation is initiated from within flash memory, all timing

is controlled by the flash controller, and the CPU is held while the erase cycle completes.

1th.Disable all interrupt and watchdog

2th.Setup flash controller and erese mode

3th.Dummy write

4^th.Set LOCK=1,re-enable interrupts and watchdog

5.  Initiating an Erase from RAM

Any erase cycle may be initiated from RAM. In this case, the CPU is not  held  and can continue to execute code from RAM(CPU无需休眠)

6.  Writing flash memory

7.  Block Write

A block write cannot be initiated from within flash memory. The block write must be initiated from RAM only.

8.  Flash Memory Access During Write or Erase

When any write or any erase operation is initiated from RAM and while

BUSY=1, the CPU may not read or write to or from any flash location.

Otherwise, an access violation occurs

When a byte/word write or any erase operation is initiated from within flash memory, the flash controller returns op-code 03FFFh to the CPU at the next instruction fetch. Op-code 03FFFh is the JMP PC instruction

9.  stopping a Write or Erase Cycle

10. Configuring and Accessing the Flash Memory Controller

11. Flash Memory Controller Interrupts

The flash controller has two interrupt sources, KEYV, and ACCVIFG.

12. Programming Flash Memory Devices

13. Flash Memory Registers

FCTL1,    FCTL2,    FCTL3,    IE1