程序功能从8bit*144的ROM中读取数据，最终组成12组，每组96bit的数据，然后再存入到96bit*12的RAM中。总是会在always和endmodule和RAM那里出错，但是又不知道怎么改！！！！求大神指教
module spmode(clk,rst,msg_96,);
input clk,rst;
output [95:0] msg_96; //96bit
output [7:0]msg8_0;
reg [7:0]adr_rom; //rom address
reg [3:0]msg_radr,msg_wadr; //ram96 read/write address
reg msg_rden,msg_wren; // enable signal
reg outfinish1,outfinish12;
reg [3:0] state_rom;
wire [7:0]q_msg8;
reg [7:0]m8_0,m8_1,m8_2,m8_3,m8_4,m8_5,m8_6,m8_7,m8_8,m8_9,m8_10,m8_11;
wire [95:0] m_96,q_msg;
rom_message rom_message(
.address(adr_rom),
.clock(clk),
.q(q_msg8));
//从ROM中读取数据
always @(posedge clk) //rom message output control
begin
if(!rst)
begin
adr_rom<=8\'d0;state_rom<=4\'d0;outfinish1<=1\'b0;outfinish12<=1\'b0;
end
else begin
if(adr_rom<144)
begin
case(state_rom)
4\'d0:begin adr_rom<=8\'d0; state_rom<=4\'d1;outfinish1<=0;outfinish12<=4\'d0;end //initilation
4\'d1:begin m8_0<=q_msg8; adr_rom<=adr_rom+8\'d1; state_rom<=4\'d2;outfinish1<=0;outfinish12<=outfinish12;end
4\'d2:begin m8_1<=q_msg8; adr_rom<=adr_rom+8\'d1; state_rom<=4\'d3;end
4\'d3:begin m8_2<=q_msg8; adr_rom<=adr_rom+8\'d1; state_rom<=4\'d4;end
4\'d4:begin m8_3<=q_msg8; adr_rom<=adr_rom+8\'d1; state_rom<=4\'d5;end
4\'d5:begin m8_4<=q_msg8; adr_rom<=adr_rom+8\'d1; state_rom<=4\'d6;end
4\'d6:begin m8_5<=q_msg8; adr_rom<=adr_rom+8\'d1; state_rom<=4\'d7;end
4\'d7:begin m8_6<=q_msg8; adr_rom<=adr_rom+8\'d1; state_rom<=4\'d8;end
4\'d8:begin m8_7<=q_msg8; adr_rom<=adr_rom+8\'d1; state_rom<=4\'d9;end
4\'d9:begin m8_8<=q_msg8; adr_rom<=adr_rom+8\'d1; state_rom<=4\'d10;end
4\'d10:begin m8_9<=q_msg8; adr_rom<=adr_rom+8\'d1; state_rom<=4\'d11;end
4\'d11:begin m8_10<=q_msg8; adr_rom<=adr_rom+8\'d1; state_rom<=4\'d12;end
4\'d12:begin m8_11<=q_msg8; adr_rom<=adr_rom+8\'d1; state_rom<=4\'d13;end
4\'d13:begin state_rom<=4\'d1; outfinish1<=1; adr_rom<=adr_rom;outfinish12<=1\'b0;end
endcase
end
else begin adr_rom<=7\'b0; outfinish12<=1\'b1; //if adr_rom>144,re-read message from rom
end
end
assign m_96={m8_0,m8_1,m8_2,m8_3,m8_4,m8_5,m8_6,m8_7,m8_8,m8_9,m8_10,m8_11};
//RAM调用，这里出现Error (10170): Verilog HDL syntax error at spmode.v(55) near text \"msg\"; expecting \"<=\", or \"=\"
真心不知道怎么改，以前也这么用，没出现过这样的问题
ram96_12 msg(.clock(clk),
.data(m_96),
.rdaddress(msg_radr),
.rden(msg_rden),
.wraddress(msg_wadr),
.wren(msg_wren),
.q(q_msg));
assign msg96=q_msg;
//控制RAM的读写使能信号，这里always出现问题
always @(posedge clk)begin
if(!rst) begin msg_rden<=1\'b0;mse_wren<=1\'b0; end
else if(outfinish1) begin msg_wren<=1\'b1; msg_rden<=1\'b0; end
else if(outfinish12) begin msg_wren<=1\'b0; msg_rden<=1\'b1; end
end
//RAM读写地址控制，还是一样的always问题
always @(posedge clk)begin
if(!rst) begin msg_radr<=4\'d0;msg_wadr<=4\'d0; end
else begin
if(msg_rden)
begin
if(msg_radr<11) msg_radr<=msg_radr+4\'d1;
else msg_radr<=4\'d0;
end
else if(msg_wren)
begin
if(msg_wadr<11) msg_wadr<=msg_wadr+4\'d1;
else msg_wadr<=4\'d0;
end
else begin msg_radr<=msg_radr;msg_wadr<=msg_wadr;end
end
end
endmodule
问题！！！！！:Mad:
Error (10170): Verilog HDL syntax error at spmode.v(55) near text \"msg\"; expecting \"<=\", or \"=\"
Error (10170): Verilog HDL syntax error at spmode.v(64) near text \"always\"; expecting \";\", or \"@\", or \"end\", or an identifier (\"always\" is a reserved keyword ), or a system task, or \"{\", or a sequential statement
Error (10170): Verilog HDL syntax error at spmode.v(72) near text \"always\"; expecting \";\", or \"@\", or \"end\", or an identifier (\"always\" is a reserved keyword ), or a system task, or \"{\", or a sequential statement
Error (10170): Verilog HDL syntax error at spmode.v(92) near text \"endmodule\"; expecting \";\", or \"@\", or \"end\", or an identifier (\"endmodule\" is a reserved keyword ), or a system task, or \"{\", or a sequential statement
就是这几个问题，begin和end都对照过，没有少啊
本文来自论坛，点击查看完整帖子内容。
