串口接收控制LED输出

//波特率产生模块

module bps_module

(

         CLK,RSTn,Bps_start,Bps_clk

);

 

input CLK;

input RSTn;

input Bps_start;

output Bps_clk;

 

reg [8:0]bps_cnt;

 

//波特率，每秒钟传输的位数

parameter bps_count=9'd434;        //波特率为115200的计数值，计算方法：（1/115200)/(1/50M),1/115200是每一位的周期

parameter bps_count_half=9'd217;//波特率为115200的计数值的一半

 

always @(posedge CLK or negedge RSTn)

begin

         if(!RSTn)

                   bps_cnt<=9'd0;

         else if(bps_cnt==bps_count||(!Bps_start))

                                     bps_cnt<=9'd0;

                            else

                                     bps_cnt<=bps_cnt+1'b1;                   //在Bps_start拉高时，bps_cnt计数

end

 

wire Bps_clk=(bps_cnt==bps_count_half)?1'b1:1'b0;//在数据位的中间点进行采样

 

endmodule

 

 

 

 

 

 

 

 

 

 

 

 

 

//串口接收模块

module rx_module

(

         CLK,RSTn,RX_in,Bps_clk,Bps_start,RX_Data

);

 

input CLK;

input RSTn;

input RX_in;

input Bps_clk;

output Bps_start;

output [7:0]RX_Data;

 

reg [1:0]detect_reg;        //用于电平检测

always @(posedge CLK or negedge RSTn)

begin

         if(!RSTn)

                   detect_reg<=2'b11;

         else

                   detect_reg<={detect_reg[0],RX_in};//********

end

 

reg rBps_start;

reg [3:0]bit_cnt;       //用于计数采样位数

wire H2L_Sig; 

assign H2L_Sig=(detect_reg==2'b10)?1'b1:1'b0;//电平由高变低（下降沿）时，H2L_Sig为1

always @(posedge CLK or negedge RSTn)

begin

         if(!RSTn)

                   rBps_start<=1'b0;

         else if(bit_cnt==4'd9)       //判断数据有没有接收完

                                     rBps_start<=1'b0;            //数据接收完，rBps_start置0

                            else if(H2L_Sig)

                                                        rBps_start<=1'b1;//下降沿到来，rBps_start置1

                                               else

                                                        rBps_start<=rBps_start;

end

 

always @(posedge CLK or negedge RSTn)

begin

         if(!RSTn)

                   bit_cnt<=4'b0;

         else if(bit_cnt==4'd9)

                                     bit_cnt<=4'd0;

                            else if(Bps_clk)

                                                        bit_cnt<=bit_cnt+1'b1;    //到达中间采样点，bit_cnt加1

                                               else

                                                        bit_cnt<=bit_cnt;

end

 

//在中间采样点，利用移位寄存器存储数据

reg [7:0]rRX_Data;

always @(posedge CLK or negedge RSTn)

begin

         if(!RSTn)

                   rRX_Data<=8'd0;

         else if(Bps_clk)

                                     rRX_Data<={RX_in,rRX_Data[7:1]};//********

                            else

                                     rRX_Data<=rRX_Data;

end

 

assign RX_Data=(bit_cnt==9)?rRX_Data:RX_Data;//判断数据是否接收完成，若完成输出数据

assign Bps_start=rBps_start;

 

endmodule                                                   

                                    

                  

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

module uart_rx_module

(

         CLK,RSTn,RX_in,RX_Data

);

 

input CLK;

input RSTn;

input RX_in;

output [7:0]RX_Data;

 

wire Bps_start;

wire Bps_clk;

bps_module U1

(

         .CLK(CLK),

         .RSTn(RSTn),

         .Bps_start(Bps_start),

         .Bps_clk(Bps_clk)

);

 

rx_module U2

(

         .CLK(CLK),

         .RSTn(RSTn),

         .Bps_start(Bps_start),

         .Bps_clk(Bps_clk),

         .RX_in(RX_in),

         .RX_Data(RX_Data)

);

 

Endmodule

 

 

 

 

 

 

 

 

 

 

 

 

 

//LED输出模块

module led_module

(

         CLK,RSTn,RX_Data,Led_out

);

 

input CLK;

input RSTn;

input [7:0]RX_Data;

output [3:0]Led_out;

 

reg [3:0]rLed_out;

 

always @(posedge CLK or negedge RSTn)

begin

         if(!RSTn)

                   rLed_out<=4'd0;

         else

                   rLed_out<=RX_Data[3:0];

end

 

assign Led_out=rLed_out;

 

endmodule

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

module uart_led_test

(

         CLK,RSTn,RX_in,Led_out

);

 

input CLK;

input RSTn;

input RX_in;

output [3:0]Led_out;

 

wire [7:0]RX_Data;

uart_rx_module U1

(

         .CLK(CLK),

         .RSTn(RSTn),

         .RX_in(RX_in),

         .RX_Data(RX_Data)

);

 

led_module U2

(

         .CLK(CLK),

         .RSTn(RSTn),

         .RX_Data(RX_Data),

         .Led_out(Led_out)

);

 

endmodule