Network protocol and system knowledge highly desirable (Ethernet, IP, ATM, SONET, DSL, EPON/GPON) Complete asic design/verification cycle from spec to product Test bench and test case development using Vera/SpecmanE/SystemVerilog/Verilog/script is required Understanding of Coverage tools Understanding of DFT/Test vector generation/debugging Understanding of Gate Level simulation Knowledge of Serdes, DDR memory, SOC/CPU, interfaces is big plus Documentation in English is highly desirable Detail and discipline oriented Experience in leading in verification of complex chips
Junior Level Verificaton engineer
Detail and discipline oriented, team work oriented Understanding of ASIC/FPGA design/verification flow Familiar with some of the EDA tool such as Verilog/VCS, Synthesis, Timing Analysis, DFT, FPGA is required Network protocol and system knowledge highly desirable (Ethernet, IP, ATM, SONET, DSL, EPON/GPON) Strong skill in C/C++ UNIX scripting is desired
