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Kentec LCD(SSD2119, 320*240) 驱动开发----基于CoX库

已有 3270 次阅读2012-12-21 09:38 |

前几天拿到了一个3.5"的屏，驱动芯片是SSD2119，芯片手册可以在网上下载，从手册中可知其支持9种接口，主要是6800、8080、SPI、RGB这四种形式，为了兼容这些接口，采用了宏定义的方式来解决：

#define SSD2119_INTERFACE_8080_8BIT   1
//#define SSD2119_INTERFACE_8080_9BIT   1
//#define SSD2119_INTERFACE_8080_16BIT 1
//#define SSD2119_INTERFACE_8080_18BIT 1
//#define SSD2119_INTERFACE_6800_8BIT   1
//#define SSD2119_INTERFACE_6800_9BIT   1
//#define SSD2119_INTERFACE_6800_16BIT 1
//#define SSD2119_INTERFACE_6800_18BIT 1
//#define SSD2119_INTERFACE_RGB_6BIT    1
//#define SSD2119_INTERFACE_RGB_18BIT   1
//#define SSD2119_INTERFACE_3SPI        1
//#define SSD2119_INTERFACE_4SPI        1

需要哪种接口，释放该对应的宏定义，同时注释掉其他的。

同样为了开发底层简单以及便于在M3/M0/M4/M0+这些内核芯片上平滑移植，我使用了CooCox开发的一套CoX库。该库可以提高开发者的效率，降低入门门槛。软件平台使用同样是CooCox推出的CoIDE编译器，操作非常简单。下面以8080、8bit为例来说明。

1、定义端口

#define SSD2119_PIN_D17         PD7
#define SSD2119_PIN_D16         PD6
#define SSD2119_PIN_D15         PD5
#define SSD2119_PIN_D14         PD4
#define SSD2119_PIN_D13         PD3
#define SSD2119_PIN_D12         PD2
#define SSD2119_PIN_D11         PD1
#define SSD2119_PIN_D10         PD0

#define SSD2119_PIN_DC PH7
#define SSD2119_PIN_CS PF3

#define SSD2119_PIN_WR PH6
#define SSD2119_PIN_RD PB5

#define SSD2119_PIN_RST PB7
#define SSD2119_PIN_BACKLIGHT PB6

2、端口初始化

    xSysCtlPeripheralEnable(xGPIOSPinToPeripheralId(SSD2119_PIN_RD));
    xSysCtlPeripheralEnable(xGPIOSPinToPeripheralId(SSD2119_PIN_WR));
    xSysCtlPeripheralEnable(xGPIOSPinToPeripheralId(SSD2119_PIN_CS));
    xSysCtlPeripheralEnable(xGPIOSPinToPeripheralId(SSD2119_PIN_DC));
    xSysCtlPeripheralEnable(xGPIOSPinToPeripheralId(SSD2119_PIN_D17));
    xSysCtlPeripheralEnable(xGPIOSPinToPeripheralId(SSD2119_PIN_D16));
    xSysCtlPeripheralEnable(xGPIOSPinToPeripheralId(SSD2119_PIN_D15));
    xSysCtlPeripheralEnable(xGPIOSPinToPeripheralId(SSD2119_PIN_D14));
    xSysCtlPeripheralEnable(xGPIOSPinToPeripheralId(SSD2119_PIN_D13));
    xSysCtlPeripheralEnable(xGPIOSPinToPeripheralId(SSD2119_PIN_D12));
    xSysCtlPeripheralEnable(xGPIOSPinToPeripheralId(SSD2119_PIN_D11));
    xSysCtlPeripheralEnable(xGPIOSPinToPeripheralId(SSD2119_PIN_D10));

xGPIOSPinTypeGPIOOutput(SSD2119_PIN_RD);
xGPIOSPinTypeGPIOOutput(SSD2119_PIN_WR);

    xGPIOSPinTypeGPIOOutput(SSD2119_PIN_CS);
    xGPIOSPinTypeGPIOOutput(SSD2119_PIN_DC);
    xGPIOSPinTypeGPIOOutput(SSD2119_PIN_D17);
    xGPIOSPinTypeGPIOOutput(SSD2119_PIN_D16);
    xGPIOSPinTypeGPIOOutput(SSD2119_PIN_D15);
    xGPIOSPinTypeGPIOOutput(SSD2119_PIN_D14);
    xGPIOSPinTypeGPIOOutput(SSD2119_PIN_D13);
    xGPIOSPinTypeGPIOOutput(SSD2119_PIN_D12);
    xGPIOSPinTypeGPIOOutput(SSD2119_PIN_D11);
    xGPIOSPinTypeGPIOOutput(SSD2119_PIN_D10);

    xGPIOSPinTypeGPIOOutput(SSD2119_PIN_RST);
    xGPIOSPinTypeGPIOOutput(SSD2119_PIN_BACKLIGHT);
    //
    // Turn on the backlight.
    //
    xGPIOSPinWrite(SSD2119_PIN_BACKLIGHT, SSD2119_BACKLIGHT_ON);

3、LCD初始化(正在开发中……)

……

经过几天的开发，终于完成了LCD的驱动，但是该论坛不支持附件上传或者是我操作不到，若需要可直接邮件联系我:machunyu@coocox.com

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回复 mcy_cool 2012-12-24 08:50: void
SSD2119Write(unsigned char ucDC, unsigned long ulInstruction, unsigned char ucRegType)
{
//
// Check Arguments.
//
xASSERT((ucDC == SSD2119_DC_COMMAND) || (ucDC == SSD2119_DC_DATA));
xASSERT((ucRegType == SSD2119_NORMAL_REG) || (ucRegType == SSD2119_GRAM_REG));

#if (defined SSD2119_INTERFACE_LEN_8BIT)
//
// DC:Command, CS:Select
//
xGPIOSPinWrite(SSD2119_PIN_CS, SSD2119_CS_ENABLE);
#ifdef  SSD2119_INTERFACE_CTL_6800
xGPIOSPinWrite(SSD2119_PIN_E, SSD2119_6800_E_ENABLE);
xGPIOSPinWrite(SSD2119_PIN_RW, SSD2119_6800_RW_WRITE);
#endif
xGPIOSPinWrite(SSD2119_PIN_DC, ucDC);

if(ucRegType == SSD2119_NORMAL_REG)
{
      xGPIOSPinWrite(SSD2119_PIN_D17, (ulInstruction >> 15) & 0x01);
      xGPIOSPinWrite(SSD2119_PIN_D16, (ulInstruction >> 14) & 0x01);
      xGPIOSPinWrite(SSD2119_PIN_D15, (ulInstruction >> 13) & 0x01);
      xGPIOSPinWrite(SSD2119_PIN_D14, (ulInstruction >> 12) & 0x01);
      xGPIOSPinWrite(SSD2119_PIN_D13, (ulInstruction >> 11) & 0x01);
      xGPIOSPinWrite(SSD2119_PIN_D12, (ulInstruction >> 10) & 0x01);
      xGPIOSPinWrite(SSD2119_PIN_D11, (ulInstruction >> 9) & 0x01);
      xGPIOSPinWrite(SSD2119_PIN_D10, (ulInstruction >> 8) & 0x01);
#ifdef SSD2119_INTERFACE_CTL_8080
      xGPIOSPinWrite(SSD2119_PIN_WR, SSD2119_8080_WR_ENABLE);
      xGPIOSPinWrite(SSD2119_PIN_WR, SSD2119_8080_WR_DISABLE);
#endif
#ifdef SSD2119_INTERFACE_CTL_6800
      xGPIOSPinWrite(SSD2119_PIN_E, SSD2119_6800_E_DISABLE);
      xGPIOSPinWrite(SSD2119_PIN_E, SSD2119_6800_E_ENABLE);
#endif
      xGPIOSPinWrite(SSD2119_PIN_D17, (ulInstruction >> 7) & 0x01);
      xGPIOSPinWrite(SSD2119_PIN_D16, (ulInstruction >> 6) & 0x01);
      xGPIOSPinWrite(SSD2119_PIN_D15, (ulInstruction >> 5) & 0x01);
      xGPIOSPinWrite(SSD2119_PIN_D14, (ulInstruction >> 4) & 0x01);
      xGPIOSPinWrite(SSD2119_PIN_D13, (ulInstruction >> 3) & 0x01);
      xGPIOSPinWrite(SSD2119_PIN_D12, (ulInstruction >> 2) & 0x01);
      xGPIOSPinWrite(SSD2119_PIN_D11, (ulInstruction >> 1) & 0x01);
      xGPIOSPinWrite(SSD2119_PIN_D10, ulInstruction & 0x01);
#ifdef SSD2119_INTERFACE_CTL_8080
      xGPIOSPinWrite(SSD2119_PIN_WR, SSD2119_8080_WR_ENABLE);
      xGPIOSPinWrite(SSD2119_PIN_WR, SSD2119_8080_WR_DISABLE);
#endif
#ifdef SSD2119_INTERFACE_CTL_6800
      xGPIOSPinWrite(SSD2119_PIN_E, SSD2119_6800_E_DISABLE);
      xGPIOSPinWrite(SSD2119_PIN_E, SSD2119_6800_E_ENABLE);
#endif
}
else
{
#if (SSD2119_COLOR_MODE == SSD2119_COLOR_MODE_65K)
      xGPIOSPinWrite(SSD2119_PIN_D17, (ulInstruction >> 15) & 0x01);
      xGPIOSPinWrite(SSD2119_PIN_D16, (ulInstruction >> 14) & 0x01);
      xGPIOSPinWrite(SSD2119_PIN_D15, (ulInstruction >> 13) & 0x01);
      xGPIOSPinWrite(SSD2119_PIN_D14, (ulInstruction >> 12) & 0x01);
      xGPIOSPinWrite(SSD2119_PIN_D13, (ulInstruction >> 11) & 0x01);
      xGPIOSPinWrite(SSD2119_PIN_D12, (ulInstruction >> 10) & 0x01);
      xGPIOSPinWrite(SSD2119_PIN_D11, (ulInstruction >> 9) & 0x01);
      xGPIOSPinWrite(SSD2119_PIN_D10, (ulInstruction >> 8) & 0x01);
#ifdef SSD2119_INTERFACE_CTL_8080
      xGPIOSPinWrite(SSD2119_PIN_WR, SSD2119_8080_WR_ENABLE);
      xGPIOSPinWrite(SSD2119_PIN_WR, SSD2119_8080_WR_DISABLE);
#endif
#ifdef SSD2119_INTERFACE_CTL_6800
      xGPIOSPinWrite(SSD2119_PIN_E, SSD2119_6800_E_DISABLE);
      xGPIOSPinWrite(SSD2119_PIN_E, SSD2119_6800_E_ENABLE);
#endif
      xGPIOSPinWrite(SSD2119_PIN_D17, (ulInstruction >> 7) & 0x01);
      xGPIOSPinWrite(SSD2119_PIN_D16, (ulInstruction >> 6) & 0x01);
      xGPIOSPinWrite(SSD2119_PIN_D15, (ulInstruction >> 5) & 0x01);
      xGPIOSPinWrite(SSD2119_PIN_D14, (ulInstruction >> 4) & 0x01);
      xGPIOSPinWrite(SSD2119_PIN_D13, (ulInstruction >> 3) & 0x01);
      xGPIOSPinWrite(SSD2119_PIN_D12, (ulInstruction >> 2) & 0x01);
      xGPIOSPinWrite(SSD2119_PIN_D11, (ulInstruction >> 1) & 0x01);
      xGPIOSPinWrite(SSD2119_PIN_D10, ulInstruction & 0x01);
#ifdef SSD2119_INTERFACE_CTL_8080
      xGPIOSPinWrite(SSD2119_PIN_WR, SSD2119_8080_WR_ENABLE);
      xGPIOSPinWrite(SSD2119_PIN_WR, SSD2119_8080_WR_DISABLE);
#endif
#ifdef SSD2119_INTERFACE_CTL_6800
      xGPIOSPinWrite(SSD2119_PIN_E, SSD2119_6800_E_DISABLE);
      xGPIOSPinWrite(SSD2119_PIN_E, SSD2119_6800_E_ENABLE);
#endif
#endif
#if (SSD2119_COLOR_MODE == SSD2119_COLOR_MODE_262K)
      xGPIOSPinWrite(SSD2119_PIN_D17, (ulInstruction >> 17) & 0x01);
      xGPIOSPinWrite(SSD2119_PIN_D16, (ulInstruction >> 16) & 0x01);
      xGPIOSPinWrite(SSD2119_PIN_D15, (ulInstruction >> 15) & 0x01);
      xGPIOSPinWrite(SSD2119_PIN_D14, (ulInstruction >> 14) & 0x01);
      xGPIOSPinWrite(SSD2119_PIN_D13, (ulInstruction >> 13) & 0x01);
      xGPIOSPinWrite(SSD2119_PIN_D12, (ulInstruction >> 12) & 0x01);
#ifdef SSD2119_INTERFACE_CTL_8080
      xGPIOSPinWrite(SSD2119_PIN_WR, SSD2119_8080_WR_ENABLE);
      xGPIOSPinWrite(SSD2119_PIN_WR, SSD2119_8080_WR_DISABLE);
#endif
#ifdef SSD2119_INTERFACE_CTL_6800
      xGPIOSPinWrite(SSD2119_PIN_E, SSD2119_6800_E_DISABLE);
      xGPIOSPinWrite(SSD2119_PIN_E, SSD2119_6800_E_ENABLE);
#endif
      xGPIOSPinWrite(SSD2119_PIN_D17, (ulInstruction >> 11) & 0x01);
      xGPIOSPinWrite(SSD2119_PIN_D16, (ulInstruction >> 10) & 0x01);
      xGPIOSPinWrite(SSD2119_PIN_D15, (ulInstruction >> 9) & 0x01);
      xGPIOSPinWrite(SSD2119_PIN_D14, (ulInstruction >> 8) & 0x01);
      xGPIOSPinWrite(SSD2119_PIN_D13, (ulInstruction >> 7) & 0x01);
      xGPIOSPinWrite(SSD2119_PIN_D12, (ulInstruction >> 6) & 0x01);
#ifdef SSD2119_INTERFACE_CTL_8080
      xGPIOSPinWrite(SSD2119_PIN_WR, SSD2119_8080_WR_ENABLE);
      xGPIOSPinWrite(SSD2119_PIN_WR, SSD2119_8080_WR_DISABLE);
#endif
#ifdef SSD2119_INTERFACE_CTL_6800
      xGPIOSPinWrite(SSD2119_PIN_E, SSD2119_6800_E_DISABLE);
      xGPIOSPinWrite(SSD2119_PIN_E, SSD2119_6800_E_ENABLE);
#endif
      xGPIOSPinWrite(SSD2119_PIN_D17, (ulInstruction >> 5) & 0x01);
      xGPIOSPinWrite(SSD2119_PIN_D16, (ulInstruction >> 4) & 0x01);
      xGPIOSPinWrite(SSD2119_PIN_D15, (ulInstruction >> 3) & 0x01);
      xGPIOSPinWrite(SSD2119_PIN_D14, (ulInstruction >> 2) & 0x01);
      xGPIOSPinWrite(SSD2119_PIN_D13, (ulInstruction >> 1) & 0x01);
      xGPIOSPinWrite(SSD2119_PIN_D12, ulInstruction & 0x01);
#ifdef SSD2119_INTERFACE_CTL_8080
      xGPIOSPinWrite(SSD2119_PIN_WR, SSD2119_8080_WR_ENABLE);
      xGPIOSPinWrite(SSD2119_PIN_WR, SSD2119_8080_WR_DISABLE);
#endif
#ifdef SSD2119_INTERFACE_CTL_6800
      xGPIOSPinWrite(SSD2119_PIN_E, SSD2119_6800_E_DISABLE);
      xGPIOSPinWrite(SSD2119_PIN_E, SSD2119_6800_E_ENABLE);
#endif
#endif
}

xGPIOSPinWrite(SSD2119_PIN_CS, SSD2119_CS_DISABLE);

#elif (defined SSD2119_INTERFACE_LEN_9BIT)
xGPIOSPinWrite(SSD2119_PIN_CS, SSD2119_CS_ENABLE);
#ifdef  SSD2119_INTERFACE_CTL_6800
xGPIOSPinWrite(SSD2119_PIN_E, SSD2119_6800_E_ENABLE);
xGPIOSPinWrite(SSD2119_PIN_RW, SSD2119_6800_RW_WRITE);
#endif
xGPIOSPinWrite(SSD2119_PIN_DC, ucDC);

if(ucRegType == SSD2119_NORMAL_REG)
{
      xGPIOSPinWrite(SSD2119_PIN_D17, (ulInstruction >> 15) & 0x01);
      xGPIOSPinWrite(SSD2119_PIN_D16, (ulInstruction >> 14) & 0x01);
      xGPIOSPinWrite(SSD2119_PIN_D15, (ulInstruction >> 13) & 0x01);
      xGPIOSPinWrite(SSD2119_PIN_D14, (ulInstruction >> 12) & 0x01);
      xGPIOSPinWrite(SSD2119_PIN_D13, (ulInstruction >> 11) & 0x01);
      xGPIOSPinWrite(SSD2119_PIN_D12, (ulInstruction >> 10) & 0x01);
      xGPIOSPinWrite(SSD2119_PIN_D11, (ulInstruction >> 9) & 0x01);
      xGPIOSPinWrite(SSD2119_PIN_D10, (ulInstruction >> 8) & 0x01);
}
else
{
      xGPIOSPinWrite(SSD2119_PIN_D17, (ulInstruction >> 17) & 0x01);
      xGPIOSPinWrite(SSD2119_PIN_D16, (ulInstruction >> 16) & 0x01);
      xGPIOSPinWrite(SSD2119_PIN_D15, (ulInstruction >> 15) & 0x01);
      xGPIOSPinWrite(SSD2119_PIN_D14, (ulInstruction >> 14) & 0x01);
      xGPIOSPinWrite(SSD2119_PIN_D13, (ulInstruction >> 13) & 0x01);
      xGPIOSPinWrite(SSD2119_PIN_D12, (ulInstruction >> 12) & 0x01);
      xGPIOSPinWrite(SSD2119_PIN_D11, (ulInstruction >> 11) & 0x01);
      xGPIOSPinWrite(SSD2119_PIN_D10, (ulInstruction >> 10) & 0x01);
      xGPIOSPinWrite(SSD2119_PIN_D9, (ulInstruction >> 9) & 0x01);
}
#ifdef SSD2119_INTERFACE_CTL_8080
xGPIOSPinWrite(SSD2119_PIN_WR, SSD2119_8080_WR_ENABLE);
xGPIOSPinWrite(SSD2119_PIN_WR, SSD2119_8080_WR_DISABLE);
#endif
#ifdef SSD2119_INTERFACE_CTL_6800
xGPIOSPinWrite(SSD2119_PIN_E, SSD2119_6800_E_DISABLE);
xGPIOSPinWrite(SSD2119_PIN_E, SSD2119_6800_E_ENABLE);
#endif

if(ucRegType == SSD2119_NORMAL_REG)
{
      xGPIOSPinWrite(SSD2119_PIN_D17, (ulInstruction >> 7) & 0x01);
      xGPIOSPinWrite(SSD2119_PIN_D16, (ulInstruction >> 6) & 0x01);
      xGPIOSPinWrite(SSD2119_PIN_D15, (ulInstruction >> 5) & 0x01);
      xGPIOSPinWrite(SSD2119_PIN_D14, (ulInstruction >> 4) & 0x01);
      xGPIOSPinWrite(SSD2119_PIN_D13, (ulInstruction >> 3) & 0x01);
      xGPIOSPinWrite(SSD2119_PIN_D12, (ulInstruction >> 2) & 0x01);
      xGPIOSPinWrite(SSD2119_PIN_D11, (ulInstruction >> 1) & 0x01);
      xGPIOSPinWrite(SSD2119_PIN_D10, ulInstruction & 0x01);
}
else
{
      xGPIOSPinWrite(SSD2119_PIN_D17, (ulInstruction >> 8) & 0x01);
      xGPIOSPinWrite(SSD2119_PIN_D16, (ulInstruction >> 7) & 0x01);
      xGPIOSPinWrite(SSD2119_PIN_D15, (ulInstruction >> 6) & 0x01);
      xGPIOSPinWrite(SSD2119_PIN_D14, (ulInstruction >> 5) & 0x01);
      xGPIOSPinWrite(SSD2119_PIN_D13, (ulInstruction >> 4) & 0x01);
      xGPIOSPinWrite(SSD2119_PIN_D12, (ulInstruction >> 3) & 0x01);
      xGPIOSPinWrite(SSD2119_PIN_D11, (ulInstruction >> 2) & 0x01);
      xGPIOSPinWrite(SSD2119_PIN_D10, (ulInstruction >> 1) & 0x01);
      xGPIOSPinWrite(SSD2119_PIN_D9, ulInstruction & 0x01);
}
#ifdef SSD2119_INTERFACE_CTL_8080
xGPIOSPinWrite(SSD2119_PIN_WR, SSD2119_8080_WR_ENABLE);
xGPIOSPinWrite(SSD2119_PIN_WR, SSD2119_8080_WR_DISABLE);
#endif
#ifdef SSD2119_INTERFACE_CTL_6800
xGPIOSPinWrite(SSD2119_PIN_E, SSD2119_6800_E_DISABLE);
xGPIOSPinWrite(SSD2119_PIN_E, SSD2119_6800_E_ENABLE);
#endif

xGPIOSPinWrite(SSD2119_PIN_CS, SSD2119_CS_DISABLE);

#elif (defined SSD2119_INTERFACE_LEN_16BIT)
xGPIOSPinWrite(SSD2119_PIN_CS, SSD2119_CS_ENABLE);
xGPIOSPinWrite(SSD2119_PIN_DC, ucDC);
#ifdef SSD2119_INTERFACE_CTL_6800
xGPIOSPinWrite(SSD2119_PIN_E, SSD2119_6800_E_ENABLE);
xGPIOSPinWrite(SSD2119_PIN_RW, SSD2119_6800_RW_WRITE);
#endif
if(ucRegType == SSD2119_NORMAL_REG)
{
      xGPIOSPinWrite(SSD2119_PIN_D17, (ulInstruction >> 15) & 0x01);
      xGPIOSPinWrite(SSD2119_PIN_D16, (ulInstruction >> 14) & 0x01);
      xGPIOSPinWrite(SSD2119_PIN_D15, (ulInstruction >> 13) & 0x01);
      xGPIOSPinWrite(SSD2119_PIN_D14, (ulInstruction >> 12) & 0x01);
      xGPIOSPinWrite(SSD2119_PIN_D13, (ulInstruction >> 11) & 0x01);
      xGPIOSPinWrite(SSD2119_PIN_D12, (ulInstruction >> 10) & 0x01);
      xGPIOSPinWrite(SSD2119_PIN_D11, (ulInstruction >> 9) & 0x01);
      xGPIOSPinWrite(SSD2119_PIN_D10, (ulInstruction >> 8) & 0x01);
      xGPIOSPinWrite(SSD2119_PIN_D8, (ulInstruction >> 7) & 0x01);
      xGPIOSPinWrite(SSD2119_PIN_D7, (ulInstruction >> 6) & 0x01);
      xGPIOSPinWrite(SSD2119_PIN_D6, (ulInstruction >> 5) & 0x01);
      xGPIOSPinWrite(SSD2119_PIN_D5, (ulInstruction >> 4) & 0x01);
      xGPIOSPinWrite(SSD2119_PIN_D4, (ulInstruction >> 3) & 0x01);
      xGPIOSPinWrite(SSD2119_PIN_D3, (ulInstruction >> 2) & 0x01);
      xGPIOSPinWrite(SSD2119_PIN_D2, (ulInstruction >> 1) & 0x01);
      xGPIOSPinWrite(SSD2119_PIN_D1, ulInstruction & 0x01);
#ifdef SSD2119_INTERFACE_CTL_8080
      xGPIOSPinWrite(SSD2119_PIN_WR, SSD2119_8080_WR_ENABLE);
      xGPIOSPinWrite(SSD2119_PIN_WR, SSD2119_8080_WR_DISABLE);
#endif
#ifdef SSD2119_INTERFACE_CTL_6800
      xGPIOSPinWrite(SSD2119_PIN_E, SSD2119_6800_E_DISABLE);
      xGPIOSPinWrite(SSD2119_PIN_E, SSD2119_6800_E_ENABLE);
#endif
}
else
{
#if (SSD2119_COLOR_MODE == SSD2119_COLOR_MODE_65K)
      xGPIOSPinWrite(SSD2119_PIN_D17, (ulInstruction >> 15) & 0x01);
      xGPIOSPinWrite(SSD2119_PIN_D16, (ulInstruction >> 14) & 0x01);
      xGPIOSPinWrite(SSD2119_PIN_D15, (ulInstruction >> 13) & 0x01);
      xGPIOSPinWrite(SSD2119_PIN_D14, (ulInstruction >> 12) & 0x01);
      xGPIOSPinWrite(SSD2119_PIN_D13, (ulInstruction >> 11) & 0x01);
      xGPIOSPinWrite(SSD2119_PIN_D12, (ulInstruction >> 10) & 0x01);
      xGPIOSPinWrite(SSD2119_PIN_D11, (ulInstruction >> 9) & 0x01);
      xGPIOSPinWrite(SSD2119_PIN_D10, (ulInstruction >> 8) & 0x01);
      xGPIOSPinWrite(SSD2119_PIN_D8, (ulInstruction >> 7) & 0x01);
      xGPIOSPinWrite(SSD2119_PIN_D7, (ulInstruction >> 6) & 0x01);
      xGPIOSPinWrite(SSD2119_PIN_D6, (ulInstruction >> 5) & 0x01);
      xGPIOSPinWrite(SSD2119_PIN_D5, (ulInstruction >> 4) & 0x01);
      xGPIOSPinWrite(SSD2119_PIN_D4, (ulInstruction >> 3) & 0x01);
      xGPIOSPinWrite(SSD2119_PIN_D3, (ulInstruction >> 2) & 0x01);
      xGPIOSPinWrite(SSD2119_PIN_D2, (ulInstruction >> 1) & 0x01);
      xGPIOSPinWrite(SSD2119_PIN_D1, ulInstruction & 0x01);
#ifdef SSD2119_INTERFACE_CTL_8080
      xGPIOSPinWrite(SSD2119_PIN_WR, SSD2119_8080_WR_ENABLE);
      xGPIOSPinWrite(SSD2119_PIN_WR, SSD2119_8080_WR_DISABLE);
#endif
#ifdef SSD2119_INTERFACE_CTL_6800
      xGPIOSPinWrite(SSD2119_PIN_E, SSD2119_6800_E_DISABLE);
      xGPIOSPinWrite(SSD2119_PIN_E, SSD2119_6800_E_ENABLE);
#endif
#endif
#if (SSD2119_COLOR_MODE == SSD2119_COLOR_MODE_262K)
      xGPIOSPinWrite(SSD2119_PIN_D17, (ulInstruction >> 17) & 0x01);
      xGPIOSPinWrite(SSD2119_PIN_D16, (ulInstruction >> 16) & 0x01);
      xGPIOSPinWrite(SSD2119_PIN_D15, (ulInstruction >> 15) & 0x01);
      xGPIOSPinWrite(SSD2119_PIN_D14, (ulInstruction >> 14) & 0x01);
      xGPIOSPinWrite(SSD2119_PIN_D13, (ulInstruction >> 13) & 0x01);
      xGPIOSPinWrite(SSD2119_PIN_D12, (ulInstruction >> 12) & 0x01);
#ifdef SSD2119_INTERFACE_CTL_8080
      xGPIOSPinWrite(SSD2119_PIN_WR, SSD2119_8080_WR_ENABLE);
      xGPIOSPinWrite(SSD2119_PIN_WR, SSD2119_8080_WR_DISABLE);
#endif
#ifdef SSD2119_INTERFACE_CTL_6800
      xGPIOSPinWrite(SSD2119_PIN_E, SSD2119_6800_E_DISABLE);
      xGPIOSPinWrite(SSD2119_PIN_E, SSD2119_6800_E_ENABLE);
#endif
      xGPIOSPinWrite(SSD2119_PIN_D8, (ulInstruction >> 11) & 0x01);
      xGPIOSPinWrite(SSD2119_PIN_D7, (ulInstruction >> 10) & 0x01);
      xGPIOSPinWrite(SSD2119_PIN_D6, (ulInstruction >> 9) & 0x01);
      xGPIOSPinWrite(SSD2119_PIN_D5, (ulInstruction >> 8) & 0x01);
      xGPIOSPinWrite(SSD2119_PIN_D4, (ulInstruction >> 7) & 0x01);
      xGPIOSPinWrite(SSD2119_PIN_D3, (ulInstruction >> 6) & 0x01);
#ifdef SSD2119_INTERFACE_CTL_8080
      xGPIOSPinWrite(SSD2119_PIN_WR, SSD2119_8080_WR_ENABLE);
      xGPIOSPinWrite(SSD2119_PIN_WR, SSD2119_8080_WR_DISABLE);
#endif
#ifdef SSD2119_INTERFACE_CTL_6800
      xGPIOSPinWrite(SSD2119_PIN_E, SSD2119_6800_E_DISABLE);
      xGPIOSPinWrite(SSD2119_PIN_E, SSD2119_6800_E_ENABLE);
#endif
      xGPIOSPinWrite(SSD2119_PIN_D17, (ulInstruction >> 5) & 0x01);
      xGPIOSPinWrite(SSD2119_PIN_D16, (ulInstruction >> 4) & 0x01);
      xGPIOSPinWrite(SSD2119_PIN_D15, (ulInstruction >> 3) & 0x01);
      xGPIOSPinWrite(SSD2119_PIN_D14, (ulInstruction >> 2) & 0x01);
      xGPIOSPinWrite(SSD2119_PIN_D13, (ulInstruction >> 1) & 0x01);
      xGPIOSPinWrite(SSD2119_PIN_D12, ulInstruction & 0x01);
#ifdef SSD2119_INTERFACE_CTL_8080
      xGPIOSPinWrite(SSD2119_PIN_WR, SSD2119_8080_WR_ENABLE);
      xGPIOSPinWrite(SSD2119_PIN_WR, SSD2119_8080_WR_DISABLE);
#endif
#ifdef SSD2119_INTERFACE_CTL_6800
      xGPIOSPinWrite(SSD2119_PIN_E, SSD2119_6800_E_DISABLE);
      xGPIOSPinWrite(SSD2119_PIN_E, SSD2119_6800_E_ENABLE);
#endif
#endif
}
xGPIOSPinWrite(SSD2119_PIN_CS, SSD2119_CS_DISABLE);

#elif (defined SSD2119_INTERFACE_LEN_18BIT)
xGPIOSPinWrite(SSD2119_PIN_CS, SSD2119_CS_ENABLE);
xGPIOSPinWrite(SSD2119_PIN_DC, ucDC);
#ifdef SSD2119_INTERFACE_CTL_6800
xGPIOSPinWrite(SSD2119_PIN_E, SSD2119_6800_E_ENABLE);
xGPIOSPinWrite(SSD2119_PIN_RW, SSD2119_6800_RW_WRITE);
#endif
if(ucRegType == SSD2119_NORMAL_REG)
{
      xGPIOSPinWrite(SSD2119_PIN_D17, (ulInstruction >> 15) & 0x01);
      xGPIOSPinWrite(SSD2119_PIN_D16, (ulInstruction >> 14) & 0x01);
      xGPIOSPinWrite(SSD2119_PIN_D15, (ulInstruction >> 13) & 0x01);
      xGPIOSPinWrite(SSD2119_PIN_D14, (ulInstruction >> 12) & 0x01);
      xGPIOSPinWrite(SSD2119_PIN_D13, (ulInstruction >> 11) & 0x01);
      xGPIOSPinWrite(SSD2119_PIN_D12, (ulInstruction >> 10) & 0x01);
      xGPIOSPinWrite(SSD2119_PIN_D11, (ulInstruction >> 9) & 0x01);
      xGPIOSPinWrite(SSD2119_PIN_D10, (ulInstruction >> 8) & 0x01);
      xGPIOSPinWrite(SSD2119_PIN_D8, (ulInstruction >> 7) & 0x01);
      xGPIOSPinWrite(SSD2119_PIN_D7, (ulInstruction >> 6) & 0x01);
      xGPIOSPinWrite(SSD2119_PIN_D6, (ulInstruction >> 5) & 0x01);
      xGPIOSPinWrite(SSD2119_PIN_D5, (ulInstruction >> 4) & 0x01);
      xGPIOSPinWrite(SSD2119_PIN_D4, (ulInstruction >> 3) & 0x01);
      xGPIOSPinWrite(SSD2119_PIN_D3, (ulInstruction >> 2) & 0x01);
      xGPIOSPinWrite(SSD2119_PIN_D2, (ulInstruction >> 1) & 0x01);
      xGPIOSPinWrite(SSD2119_PIN_D1, ulInstruction & 0x01);
}
else
{
      xGPIOSPinWrite(SSD2119_PIN_D17, (ulInstruction >> 17) & 0x01);
      xGPIOSPinWrite(SSD2119_PIN_D16, (ulInstruction >> 16) & 0x01);
      xGPIOSPinWrite(SSD2119_PIN_D15, (ulInstruction >> 15) & 0x01);
      xGPIOSPinWrite(SSD2119_PIN_D14, (ulInstruction >> 14) & 0x01);
      xGPIOSPinWrite(SSD2119_PIN_D13, (ulInstruction >> 13) & 0x01);
      xGPIOSPinWrite(SSD2119_PIN_D12, (ulInstruction >> 12) & 0x01);
      xGPIOSPinWrite(SSD2119_PIN_D11, (ulInstruction >> 11) & 0x01);
      xGPIOSPinWrite(SSD2119_PIN_D10, (ulInstruction >> 10) & 0x01);
      xGPIOSPinWrite(SSD2119_PIN_D9, (ulInstruction >> 9) & 0x01);
      xGPIOSPinWrite(SSD2119_PIN_D8, (ulInstruction >> 8) & 0x01);
      xGPIOSPinWrite(SSD2119_PIN_D7, (ulInstruction >> 7) & 0x01);
      xGPIOSPinWrite(SSD2119_PIN_D6, (ulInstruction >> 6) & 0x01);
      xGPIOSPinWrite(SSD2119_PIN_D5, (ulInstruction >> 5) & 0x01);
      xGPIOSPinWrite(SSD2119_PIN_D4, (ulInstruction >> 4) & 0x01);
      xGPIOSPinWrite(SSD2119_PIN_D3, (ulInstruction >> 3) & 0x01);
      xGPIOSPinWrite(SSD2119_PIN_D2, (ulInstruction >> 2) & 0x01);
      xGPIOSPinWrite(SSD2119_PIN_D1, (ulInstruction >> 1) & 0x01);
      xGPIOSPinWrite(SSD2119_PIN_D0, ulInstruction & 0x01);
}
#ifdef SSD2119_INTERFACE_CTL_8080
xGPIOSPinWrite(SSD2119_PIN_WR, SSD2119_8080_WR_ENABLE);
xGPIOSPinWrite(SSD2119_PIN_WR, SSD2119_8080_WR_DISABLE);
#endif
#ifdef SSD2119_INTERFACE_CTL_6800
xGPIOSPinWrite(SSD2119_PIN_E, SSD2119_6800_E_DISABLE);
xGPIOSPinWrite(SSD2119_PIN_E, SSD2119_6800_E_ENABLE);
#endif

xGPIOSPinWrite(SSD2119_PIN_CS, SSD2119_CS_DISABLE);

#elif (defined SSD2119_INTERFACE_18RGB)

#elif (defined SSD2119_INTERFACE_3_SPI)
if(ucDC)
{
      if(ucRegType == SSD2119_NORMAL_REG)
      {
         xSPIDataBufferWriteNonBlocking(SSD2119_SPIBase, ((ulInstruction >> 8) & 0xFF) | 0x100);
         xSPIDataBufferWriteNonBlocking(SSD2119_SPIBase, (ulInstruction & 0xFF) | 0x100);
      }
      else
      {
         xSPIDataBufferWriteNonBlocking(SSD2119_SPIBase, ((ulInstruction >> 12) & 0xFC) | 0x100);
         xSPIDataBufferWriteNonBlocking(SSD2119_SPIBase, ((ulInstruction >> 6) & 0xFC) | 0x100);
         xSPIDataBufferWriteNonBlocking(SSD2119_SPIBase, (ulInstruction & 0xFC) | 0x100);
      }
}
else
{
      xSPIDataBufferWriteNonBlocking(SSD2119_SPIBase, ulInstruction & 0xFF);
}
#elif (defined SSD2119_INTERFACE_4_SPI)
xGPIOSPinWrite(SSD2119_PIN_DC, ucDC);
if(ucDC)
{
      if(ucRegType == SSD2119_NORMAL_REG)
      {
         xSPIDataBufferWriteNonBlocking(SSD2119_SPIBase, (ulInstruction >> 8) & 0xFF);
         xSPIDataBufferWriteNonBlocking(SSD2119_SPIBase, ulInstruction & 0xFF);
      }
      else
      {
         xSPIDataBufferWriteNonBlocking(SSD2119_SPIBase, (ulInstruction >> 12) & 0xFC);
         xSPIDataBufferWriteNonBlocking(SSD2119_SPIBase, (ulInstruction >> 6) & 0xFC);
         xSPIDataBufferWriteNonBlocking(SSD2119_SPIBase, ulInstruction & 0xFC);
      }
}
xSPIDataBufferWriteNonBlocking(SSD2119_SPIBase, ulInstruction & 0xFF);
#endif
}

以上是往LCD中写入数据或命令值，当ucDC == SSD2119_DC_COMMAND时是往寄存器中写命令，当ucDC == SSD2119_DC_DATA时写数据，因为考虑兼容了SSD2119的众多接口，所以这个程序显得非常臃肿。

回复平湖秋月 2013-6-18 01:56: 呵呵，神州行，我看行

mcy_cool