LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY mima1 IS
PORT(DATAIN:IN STD_LOGIC_VECTOR(3 DOWNTO 0);
FUNIN:IN STD_LOGIC_VECTOR(3 DOWNTO 0);
DFIN:IN STD_LOGIC;
FFIN:IN STD_LOGIC;
CLKIN:IN STD_LOGIC;
ENLOCK:OUT STD_LOGIC;
KEYBCD:OUT STD_LOGIC_VECTOR(15 DOWNTO 0));
END ENTITY mima1;
ARCHITECTURE ONE OF mima1 IS
SIGNAL ACC,REG:STD_LOGIC_VECTOR(15 DOWNTO 0);
SIGNAL NC:STD_LOGIC_VECTOR(2 DOWNTO 0);
SIGNAL RR2,BB,QA,QB:STD_LOGIC;
SIGNAL R1,R0:STD_LOGIC;
BEGIN
PROCESS(CLKIN)
BEGIN
IF CLKIN'EVENT AND CLKIN='1' THEN
R1<=R0;R0<=FFIN;
END IF;
RR2<=R1 AND NOT R0;
END PROCESS;
KEYINPUT:BLOCK IS
SIGNAL RST,D0,D1:STD_LOGIC;
BEGIN
RST<=RR2;
PROCESS(DFIN,RST)IS
BEGIN
IF RST='1'THEN
ACC<="0000000000000000";
NC<="000";
ELSE
IF DFIN'EVENT AND DFIN='1' THEN
IF NC<4 THEN
ACC<=ACC(11 DOWNTO 0)&DATAIN;
NC<=NC+1;
END IF;
END IF;
END IF;
END PROCESS;
END BLOCK KEYINPUT;
LOCKCTRL:BLOCK IS
BEGIN
PROCESS(CLKIN,FUNIN)
BEGIN
IF(CLKIN'EVENT AND CLKIN ='1')THEN
IF NC=4 THEN
IF FUNIN(2)='1'THEN
REG<=ACC;
QA<='1';QB<='0';
END IF;
ELSIF FUNIN(0)='1'THEN
IF REG=ACC THEN
QA<='0';QB<='1';
END IF;
END IF;
END IF;
END PROCESS;
END BLOCK LOCKCTRL;
ENLOCK<=QA AND NOT QB;
KEYBCD<=ACC;
END ONE;
