jk触发器

library ieee;
use ieee.std_logic_1164.all;
USE IEEE.STD_LOGIC_UNSIGNED;
entity jk is
port(R,S,j,k,cp:in std_logic;
      Q,Q1:out std_logic);
      end jk;
      architecture a of jk is
      signal tem, tmp: std_logic;
      begin
      process(R,S,j,k,cp)
      begin
      if R<='0' AND S<='1' THEN
        tem<='0'; tmp<='1';
        elsif R<='1' AND  S<='0'THEN
          tem<='1'; tmp<='0';
         elsif R<='1' AND S<='1' THEN     
      if cp'event and cp='1' then
         if j<='0' and k<='0' then
        tem<=tem; tmp<=tmp;
        elsif j<='0' and k<='1' then
        tem<='0'; tmp<='1';
        elsif j<='1' and k<='0' then
        tem<='1'; tmp<='0';
        elsif j<='1' and k<='1' then
        tem<=not tem; tmp<=not tmp;
      end if;
      end if;
      end if;
      Q<=tem;Q1<=tmp;
      end process;
      end a;