module module_name(
input clk,
input rst,
input adr;
input re,
input we,
input [7:0] data_in,
output reg [7:0] data_out
);
wire [1:0] state_a;
wire [1:0] state_b;
wire addr;
reg [1:0] sel;
reg valid;
reg [7:0] mem[255:0];
assign addr= adr;
always @(posedge clk)
begin
if ( re )
data_out <= mem[addr];
else if ( we )
mem[addr] <= data_in;
end
