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void TMR0_IRQHandler(void)
{
static uint8_t ADC_GET_Time=0;
ADC_GET_Time++;
if(ADC_GET_Time % 10==0)
{
adc_Channel=2;
//ADC0_StartConvert(ADC_CH_0, 0, 1,4); //¿aê¼ADC0×a»»
//ADC_StartConvert(ADC_CH_0_DIV_5, 0, 0);
ADC_StartConvert(ADC_CH_0, 0, 0);
ADC_GET_Time = 1;
}
else if((ADC_GET_Time % 2==0)&&(adc_Channel==0))
{
adc_Channel=1;
//ADC0_StartConvert(ADC_CH_1, 0, 1,5); //¿aê¼ADC0×a»»
ADC_StartConvert(ADC_CH_1, 0, 0);
//ADC_StartConvert(ADC_CH_1_DIV_5, 0, 0);
}
TMR32_ClearFlag(MXC_TMR0);
}
#define USE_INTERRUPTS 1
//#undef USE_INTERRUPTS
/***** Globals *****/
//#ifdef USE_INTERRUPTS
volatile unsigned int adc_Channel = 0;
//#endif
/***** Functions *****/
#ifdef USE_INTERRUPTS
void AFE_IRQHandler(void)
{
uint16_t ADC_Value_Temp=0;
ADC_GetData(&ADC_Value_Temp);
/* Signal bottom half that data is ready */
if(adc_Channel == 1)
{
//LED1_OFF;
Get_ADC1_Data(ADC_Value_Temp);
}
else if(adc_Channel == 2)
{
Get_ADC2_Data(ADC_Value_Temp);
}
adc_Channel = 0;
// LED0_TURN;
ADC_ClearFlags(MXC_F_ADC_INTR_ADC_DONE_IF);
return;
}
#endif
void ADC0_Init()
{
/* Initialize ADC */
ADC_Init();
#ifdef USE_INTERRUPTS
// NVIC_EnableIRQ(AFE_IRQn);
NVIC_ClearPendingIRQ(AFE_IRQn);
NVIC_DisableIRQ(AFE_IRQn);
NVIC_SetPriority(AFE_IRQn, 1);
NVIC_EnableIRQ(AFE_IRQn);
#endif
}
/* ************************************************************************* */
void ADC0_StartConvert(mxc_adc_chsel_t channel, unsigned int adc_scale, unsigned int bypass, uint32_t mode)
{
uint32_t ctrl_tmp;
/* Clear the ADC done flag */
ADC_ClearFlags(MXC_F_ADC_INTR_ADC_DONE_IF);
/* Enable done interrupt */
MXC_ADC->intr = MXC_F_ADC_INTR_ADC_DONE_IE;
/* Insert channel selection */
ctrl_tmp = MXC_ADC->ctrl;
ctrl_tmp &= ~(MXC_F_ADC_CTRL_ADC_CHSEL);
ctrl_tmp |= ((channel << MXC_F_ADC_CTRL_ADC_CHSEL_POS) | (mode<<MXC_F_ADC_CTRL_ADC_CHSEL_POS));
//ctrl_tmp |= ((channel << MXC_F_ADC_CTRL_ADC_CHSEL_POS) & MXC_F_ADC_CTRL_ADC_CHSEL);
/* Clear channel configuration */
ctrl_tmp &= ~(MXC_F_ADC_CTRL_ADC_REFSCL | MXC_F_ADC_CTRL_ADC_SCALE | MXC_F_ADC_CTRL_BUF_BYPASS);
/* ADC reference scaling must be set for all channels but two*/
if ((channel != ADC_CH_VDD18) && (channel != ADC_CH_VDD12)) {
ctrl_tmp |= MXC_F_ADC_CTRL_ADC_REFSCL;
}
/* Finalize user-requested channel configuration */
if (adc_scale || channel > ADC_CH_3) {
ctrl_tmp |= MXC_F_ADC_CTRL_ADC_SCALE;
}
if (bypass) {
ctrl_tmp |= MXC_F_ADC_CTRL_BUF_BYPASS;
}
/* Write this configuration */
MXC_ADC->ctrl = ctrl_tmp;
/* Start conversion */
MXC_ADC->ctrl |= MXC_F_ADC_CTRL_CPU_ADC_START;
}