<

>网上也很多,这是前一段自己写的一个:</P>
<

>--filename : main part of digital clock system<BR>--designed by : TangQF<BR>--inputs&outputs introduction:<BR>--clk_key_deal : clk_key_deal input<BR>--reset : system reset signal<BR>--key_mode : key input of the board to alter clock's work-mode<BR>--key_add : key input of the board to add the number of </P>
<

>time'second or minute or hour<BR>--key_mode_out : the key output after being delt<BR>--key_add_out : the key output after being delt<BR>--date : 2010.03.14</P>
<P>--begin of text<BR>entity key_deal is<BR>port (key_mode,key_add,clk_key_deal : in bit;<BR> key_mode_out,key_add_out : out bit);<BR>end key_deal;</P>
<P>architecture ocean of key_deal is</P>
<P>signal k00,k01 : bit;<BR>signal k10,k11 : bit;</P>
<P>begin</P>
<P>process(clk_key_deal)<BR>begin<BR>if clk_key_deal'event and clk_key_deal='1' then<BR>k00<=k01;<BR>k01<=key_mode;<BR>key_mode_out<=k00 and k01 and key_mode;</P>
<P>k10<=k11;<BR>k11<=key_add;<BR>key_add_out<=k10 and k11 and key_add;<BR>end if;<BR>end process;</P>
<P>end ocean;<BR>--the end<BR></P>