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/*
* Copyright (c) 2015, Freescale Semiconductor, Inc.
* Copyright 2016-2017 NXP
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
*
* o Redistributions of source code must retain the above copyright notice, this list
* of conditions and the following disclaimer.
*
* o Redistributions in binary form must reproduce the above copyright notice, this
* list of conditions and the following disclaimer in the documentation and/or
* other materials provided with the distribution.
*
* o Neither the name of the copyright holder nor the names of its
* contributors may be used to endorse or promote products derived from this
* software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
/*
* TEXT BELOW IS USED AS SETTING FOR THE PINS TOOL *****************************
PinsProfile:
- !!product 'Pins v2.0'
- !!processor 'MKW41Z512xxx4'
- !!package 'MKW41Z512VHT4'
- !!mcu_data 'ksdk2_0'
- !!processor_version '0.0.0'
* BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR THE PINS TOOL ***
*/
#include "fsl_common.h"
#include "fsl_port.h"
#include "pin_mux.h"
#define PIN6_IDX 6u /*!< Pin number for pin 6 in a port */
#define PIN7_IDX 7u /*!< Pin number for pin 7 in a port */
#define PIN16_IDX 16u /*!< Pin number for pin 16 in a port */
#define PIN17_IDX 17u /*!< Pin number for pin 17 in a port */
#define PIN18_IDX 18u /*!< Pin number for pin 18 in a port */
#define PIN19_IDX 19u /*!< Pin number for pin 19 in a port */
#define SOPT5_LPUART0RXSRC_LPUART_RX 0x00u /*!< LPUART0 Receive Data Source Select: LPUART_RX pin */
/*
* TEXT BELOW IS USED AS SETTING FOR THE PINS TOOL *****************************
BOARD_InitPins:
- options: {coreID: singlecore, enableClock: 'true'}
- pin_list:
- {pin_num: '42', peripheral: LPUART0, signal: RX, pin_signal: TSI0_CH2/PTC6/LLWU_P14/XTAL_OUT_EN/I2C1_SCL/UART0_RX/TPM2_CH0/BSM_FRAME}
- {pin_num: '43', peripheral: LPUART0, signal: TX, pin_signal: TSI0_CH3/PTC7/LLWU_P15/SPI0_PCS2/I2C1_SDA/UART0_TX/TPM2_CH1/BSM_DATA}
- {pin_num: '45', peripheral: SPI0, signal: SCK, pin_signal: TSI0_CH4/PTC16/LLWU_P0/SPI0_SCK/I2C0_SDA/UART0_RTS_b/TPM0_CH3}
- {pin_num: '46', peripheral: SPI0, signal: SOUT, pin_signal: TSI0_CH5/PTC17/LLWU_P1/SPI0_SOUT/I2C1_SCL/UART0_RX/BSM_FRAME/DTM_RX}
- {pin_num: '47', peripheral: SPI0, signal: SIN, pin_signal: TSI0_CH6/PTC18/LLWU_P2/SPI0_SIN/I2C1_SDA/UART0_TX/BSM_DATA/DTM_TX}
- {pin_num: '48', peripheral: SPI0, signal: PCS0_SS, pin_signal: TSI0_CH7/PTC19/LLWU_P3/SPI0_PCS0/I2C0_SCL/UART0_CTS_b/BSM_CLK/BLE_RF_ACTIVE}
- {pin_num: '4', peripheral: SPI1, signal: SOUT, pin_signal: TSI0_CH10/PTA16/LLWU_P4/SPI1_SOUT/TPM0_CH0}
- {pin_num: '5', peripheral: SPI1, signal: SIN, pin_signal: TSI0_CH11/PTA17/LLWU_P5/RF_RESET/SPI1_SIN/TPM_CLKIN1}
- {pin_num: '6', peripheral: SPI1, signal: SCK, pin_signal: TSI0_CH12/PTA18/LLWU_P6/SPI1_SCK/TPM2_CH0}
- {pin_num: '7', peripheral: SPI1, signal: PCS0_SS, pin_signal: TSI0_CH13/ADC0_SE5/PTA19/LLWU_P7/SPI1_PCS0/TPM2_CH1}
* BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR THE PINS TOOL ***
*/
/*FUNCTION**********************************************************************
*
* Function Name : BOARD_InitPins
* Description : Configures pin routing and optionally pin electrical features.
*
*END**************************************************************************/
void BOARD_InitPins(void) {
CLOCK_EnableClock(kCLOCK_PortA); /* Port A Clock Gate Control: Clock enabled */
CLOCK_EnableClock(kCLOCK_PortC); /* Port C Clock Gate Control: Clock enabled */
PORT_SetPinMux(PORTA, PIN16_IDX, kPORT_MuxAlt2); /* PORTA16 (pin 4) is configured as SPI1_SOUT */
PORT_SetPinMux(PORTA, PIN17_IDX, kPORT_MuxAlt2); /* PORTA17 (pin 5) is configured as SPI1_SIN */
PORT_SetPinMux(PORTA, PIN18_IDX, kPORT_MuxAlt2); /* PORTA18 (pin 6) is configured as SPI1_SCK */
PORT_SetPinMux(PORTA, PIN19_IDX, kPORT_MuxAlt2); /* PORTA19 (pin 7) is configured as SPI1_PCS0 */
PORT_SetPinMux(PORTC, 4u, kPORT_MuxAsGpio); /* PORTC4 (pin 40) is configured as GPIOC4 */
PORT_SetPinMux(PORTC, 16u, kPORT_MuxAsGpio); /* PORTC16 (pin 45) is configured as GPIOC16 */
PORT_SetPinMux(PORTC, PIN6_IDX, kPORT_MuxAlt4); /* PORTC6 (pin 42) is configured as UART0_RX */
PORT_SetPinMux(PORTC, PIN7_IDX, kPORT_MuxAlt4); /* PORTC7 (pin 43) is configured as UART0_TX */
SIM->SOPT5 = ((SIM->SOPT5 &
(~(SIM_SOPT5_LPUART0RXSRC_MASK))) /* Mask bits to zero which are setting */
| SIM_SOPT5_LPUART0RXSRC(SOPT5_LPUART0RXSRC_LPUART_RX) /* LPUART0 Receive Data Source Select: LPUART_RX pin */
);
}
/*******************************************************************************
* EOF
******************************************************************************/
/*
* Copyright (c) 2013 - 2015, Freescale Semiconductor, Inc.
* Copyright 2016-2017 NXP
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
*
* o Redistributions of source code must retain the above copyright notice, this list
* of conditions and the following disclaimer.
*
* o Redistributions in binary form must reproduce the above copyright notice, this
* list of conditions and the following disclaimer in the documentation and/or
* other materials provided with the distribution.
*
* o Neither the name of the copyright holder nor the names of its
* contributors may be used to endorse or promote products derived from this
* software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#include "fsl_device_registers.h"
#include "fsl_debug_console.h"
#include "fsl_dspi.h"
#include "fsl_port.h"
#include "board.h"
#include "pin_mux.h"
#include "clock_config.h"
#include "EPD_drive.h"
#include "EPD_drive_gpio.h"
#include "Display_Lib.h"
/*******************************************************************************
* Definitions
******************************************************************************/
#define DSPI_MASTER_CLK_SRC DSPI1_CLK_SRC
#define DSPI_MASTER_CLK_FREQ CLOCK_GetFreq(DSPI1_CLK_SRC)
dspi_master_handle_t g_m_handle; //global variable
/*******************************************************************************
* Prototypes
******************************************************************************/
/*******************************************************************************
* Variables
******************************************************************************/
/*******************************************************************************
* Code
******************************************************************************/
void delay_ms(unsigned long xms)
{
volatile uint32_t i = 0;
while(xms--)
{
for (i = 0; i < 4000; ++i)
{
__asm("NOP"); /* delay */
}
}
}
/*!
* @brief Main function
*/
int main(void)
{
int tt=0;
//Define a digital output pin configuration
gpio_pin_config_t out_config =
{
kGPIO_DigitalOutput,
0,
};
//Define a digital intput pin configuration
gpio_pin_config_t in_config =
{
kGPIO_DigitalInput,
0,
};
/* Input pin PORT configuration */
port_pin_config_t config = {
kPORT_PullUp,
kPORT_FastSlewRate,
kPORT_PassiveFilterDisable,
kPORT_LowDriveStrength,
kPORT_MuxAsGpio,
};
BOARD_InitPins();
BOARD_BootClockRUN();
BOARD_InitDebugConsole();
/* Sets the configuration */
PORT_SetPinConfig(PORTC, 19, &config);
FGPIO_PinInit(FGPIOC, 19, &in_config);//D2
GPIO_PinInit(RST_GPIO_Port, RST_Pin, &out_config);//D3
GPIO_PinInit(DC_GPIO_Port, DC_Pin, &out_config);//D4
PRINTF("DSPI polling to drive the WaveShare 1.54 inch e-Paper example start.\r\n");
uint32_t srcClock_Hz;
dspi_master_config_t masterConfig;
/* Master config */
masterConfig.whichCtar = kDSPI_Ctar0;
masterConfig.ctarConfig.baudRate = 16000000U;
masterConfig.ctarConfig.bitsPerFrame = 8;
masterConfig.ctarConfig.cpol = kDSPI_ClockPolarityActiveLow;
masterConfig.ctarConfig.cpha = kDSPI_ClockPhaseFirstEdge;
masterConfig.ctarConfig.direction = kDSPI_MsbFirst;
masterConfig.ctarConfig.pcsToSckDelayInNanoSec =1;//1000000000U / masterConfig.ctarConfig.baudRate
masterConfig.ctarConfig.lastSckToPcsDelayInNanoSec = 1;
masterConfig.ctarConfig.betweenTransferDelayInNanoSec = 1;
masterConfig.whichPcs = kDSPI_Pcs0;
masterConfig.pcsActiveHighOrLow = kDSPI_PcsActiveLow;
masterConfig.enableContinuousSCK = false;
masterConfig.enableRxFifoOverWrite = false;
masterConfig.enableModifiedTimingFormat = false;
masterConfig.samplePoint = kDSPI_SckToSin0Clock;
srcClock_Hz = DSPI_MASTER_CLK_FREQ;
DSPI_MasterInit(SPI1, &masterConfig, srcClock_Hz);
DSPI_MasterTransferCreateHandle(SPI1, &g_m_handle, NULL, NULL);
PRINTF("srcClock=%d MHz\r\n",srcClock_Hz/1000000);
PRINTF("sysClock=%d MHz\r\n",CLOCK_GetFreq(kCLOCK_CoreSysClk)/1000000);
/* Start master transfer */
Dis_Clear_full();
delay_ms(500);
Dis_Clear_full();
delay_ms(500);
Dis_Clear_part();
delay_ms(500);
Dis_Clear_part();
Dis_showNum64128(32,48,00);
EPD_Dis_Part(0,0+1*24-1,0,0+48-1,Font2448[13],1);//p
EPD_Dis_Part(0+1*24,0+2*24-1,0,0+48-1,Font2448[12],1);//x
EPD_Dis_Part(0+2*24,0+3*24-1,0,0+48-1,Font2448[11],1);//n
EPD_Dis_Part(0+3*24,0+4*24-1,0,0+48-1,Font2448[16],1);//z
EPD_Dis_Part(0+4*24,0+5*24-1,0,0+48-1,Font2448[1],1);//1
EPD_Dis_Part(0+5*24,0+6*24-1,0,0+48-1,Font2448[4],1);//4
EPD_Dis_Part(0+6*24,0+7*24-1,0,0+48-1,Font2448[15],1);//w
EPD_Dis_Part(0+7*24,0+8*24-1,0,0+48-1,Font2448[14],1);//k
while (1)
{
tt++;
if(tt>99)
tt=0;
Dis_showNum64128(32,48,tt);
delay_ms(500);
}
}
dspi_transfer_t masterXfer;
extern dspi_master_handle_t g_m_handle; //global variable
void SPI_Write(unsigned char value)
{
// status_t ret=kStatus_Fail;
uint8_t TxData=value;
masterXfer.txData=&TxData;
masterXfer.dataSize=1;
masterXfer.configFlags = kDSPI_MasterPcs0;//kDSPI_MasterCtar0 | kDSPI_MasterPcs0 | kDSPI_MasterPcsContinuous
//DSPI_MasterTransferBlocking(SPI1, &masterXfer);
DSPI_MasterTransferNonBlocking(SPI1, &g_m_handle,&masterXfer);
// ret=DSPI_MasterTransferBlocking(SPI1, &masterXfer);
// if(ret!=kStatus_Success)
// {
// PRINTF("ret=%d \r\n",ret);
// }
}
