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| Dear All, 某外资公司(上海浦东）急聘Verification Engineer！！ 要求：硕士3-6年，欢迎投递简历至Jessicawu2308@hotmail.com或加QQ:3142971475进行咨询  JD如下： Position Description: ? Deliver/implement advanced verification solutions by utilizing Cadence’s Incisive Verification product portfolio. The engineer should be able to act as a strong team member and contributor, leading team projects and initiatives. Exercise judgment within generally defined practices and policies. ? Specific duties include: ? Deep understanding on ASIC design and verification flow ? Excellent knowledge of advanced verification methodology like eRM/OVM/UVM/VMM ? Familiar with Cadence’s Incisive Plan to Closure Methodology (IPCM) ? Proficiency in System Verilog, System C and/or e (Specman) ? Developing and using Verification Components (eVC, OVC,UVC,VIP) ? Developing and using assertion based verification and formal analysis methods ? Skilled in scripting language, such as Perl, C shell, Python, Make file ? Assessing the project verification requirements Position Requirements: ? BS degree with 5+ years of applicable experience, MS degree with 3+ years of applicable experience in electrical engineering, microelectronics, comparable engineering science or solid state physics. ? Essential that the individual demonstrates strong communication, verbal and written. Requires good communication skills in English. ? Will have demonstrated hands-on experience and expertise with Cadence verification design tools or equivalent tools, flows and methodologies required to execute a verification project. ? Will have demonstrated successful completion of 3+ verification projects as an individual contributor |