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ARM cortex M0 verification script --- Perl

已有 2698 次阅读2015-5-2 00:37

#!/usr/bin/perl
#################################################################################
#
# The confidential and proprietary information contained in this file may
# only be used by a person authorised under and to the extent permitted
# by a subsisting licensing agreement from ARM Limited.
#
# (C) COPYRIGHT 2009 ARM Limited.
# ALL RIGHTS RESERVED
#
# This entire notice must be reproduced on all copies of this file
# and copies of this file may only be made by a person if such person is
# permitted to do so under the terms of a subsisting license agreement
# from ARM Limited.
#
# Cortex-M0 Integration Kit Validation Script
# ===========================================
#
# SVN Information
#
# Checked In : $Date: $
#
# Revision : $Revision: $
#
# Release Information : Cortex-M0-AT510-r0p0-01rel0
#
################################################################################
# Script Usage: RunIK
################################################################################
# RunIK takes the following options
# -h : prints options usage
# -mti : use mti simulator (default)
# -nc : use nc simulator
# -vcs : use vcs simulator
# -make : use make to compile tests in the tests directory
# -build : build the RTL or netlist
# -netlist : use netlist
# /integration_kit/logical/tbench/verilog/netlist.vc
# should point to netlist file and technology libraries
# if -sdf option is not used, zero-delays are assumed
# -sdf: use SDF timing annotation with netlist
#can be "max" or "min" in uppercase or lowercase
# this option only works with -netlist option
# /integration_kit/validation/CORTEMOINTEGRATIONIMP.sdf.gz
# or /integration_kit/validation/CORTEMOIMP.sdf.gz should
# link to appropriate gzipped sdf file
# -dsm : use the DSM for CORTEXM0
# /integration_kit/logical/tbench/verilog/dsm.vc
# should point to DSM CORTEXM0
# -upf : uses power_file for simulation
# power_file points to either srpg/CORTEXM0INTEGRATONIMP.upf
# or srpg/CORTEXM0IMP.upf
# -cpf : uses power_file for simulation
# power_file points to either srpg/CORTEXM0INTEGRATONIMP.cpf
# or srpg/CORTEXM0IMP.cpf
# -all : run all tests in the perl array @testlist
#ignored
# -make with -all results in "make all". So ensure the "all" in
# Makefile includes all tests in @testlist
# -build with -all builds RTL/netlist only once
#
################################################################################
$^W=1; # enable warnings (same as perl -w)
use Cwd;
use Getopt::Long;
use File::Basename;
use File::Copy;
my @testlist = qw (dhry hellow max_power speed_indicative config_check interrupt reset sleep debug romtable); #Add tests to this array
my $prog = basename($0);
my $help;
my $make = 0;
my $build = 0;
my $level = 0;
my $netlist = 0;
my $sdf;
my $sdfset = 0;
my $dsm = 0;
my $upf = 0;
my $cpf = 0;
my $runall = 0;
my $testname;
my $default_simulator = "mti";
my $simulator;
my $cwd = cwd(); # Get current directory
my $testdir = $cwd."/tests";
my $vectdir = $cwd."/vectors";
my $logsdir = $cwd."/logs";
my $srpgdir = $cwd."/srpg";
my $rtldir = $cwd."/../../logical";
my $tbenchdir = $cwd."/../logical/tbench/verilog";
my $rundir;
my $buildopts = "";
my $ncelabopts = "-ACCESS rwc";
my $simopts = "";
my $simopts_cov = "";
my $gui = 0;
my $coverage = 0;
my $cov_mod = "cm_hier.mod";
my $dsmsetup = 1;
my $power_file = $cwd."/power_file"; #power_file must point to upf/cpf file at correct level
my $list = 0;
my $dsmlibopt = "";
my $upfopt = "";
my $vcs64 = "";
my $usage="
USAGE: $prog
Description:
whereare:
-h[elp] : print usage
-mti : use mti simulator (default)
-nc : use nc simulator
-vcs : use vcs simulator
-make : call make to compile test(s)
-build : build before running
-net

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