input CLK_IN; //40Mhz
input CLK_RST; //全局复位信号
output SYS_CLK;//输出20Mhz时钟信号
output MAC_CLK;//7.5Mhz
output DIN_CLK;//60Mhz
output CB_CLK;//80Mhz
output SYS_CLK_D;//40Mhz
output LOCKED;//时钟锁定信号，高电平锁定，锁定期间所有时钟正常工作
wire RST; //RST is the core reset signal enabled with high level
wire LOCKED_OUT1; //Output of the DCM1 that activates after the DCM has achieved lock
wire SYS_CLK; //Clock divide output of the DCM1 by 2
wire CB_CLK; //Clock double output of the DCM1
wire DCM2_CLK; //Frequency synthesizer output to the DCM1 by 2/3
wire SYS_CLK_D; //The clock output same as input clock of DCM1
wire CLK_IN2; //Clock for generating MAC_CLK
reg LOCKED;
reg MAC_CLK; //Clock divide output of the DCM1 by 8
wire DIN_CLK;
reg lock_reg;
reg lock_reg1;
reg lock_reg2;
assign DCM2_CEN=~lock_reg2;
assign RST=~CLK_RST; //RST is the core reset signal enabled with high level.
wire RST2;
assign RST2=lock_reg2;
//Digital clock management block1 is used to generate clocks with the frequency
//of 20MHz, 40MHz, 80 MHz and 60MHz. The last one will be used as the clock to
//generator 7.5MHz.
wire clk_reg;
DCM1 U_DCM1 (
.RST_IN(RST),
.LOCKED_OUT(LOCKED_OUT1),
.CLKIN_IN(CLK_IN),
.CLKDV_OUT(SYS_CLK),
.CLK2X_OUT(CB_CLK),
.CLKFX_OUT(DCM2_CLK),
.CLK0_OUT(SYS_CLK_D),
.CLKIN_IBUFG_OUT(clk_reg)
);
BUFG DCM2_CLK_BUFG(
.I (DCM2_CLK),
.O (CLK_IN2)
);
BUFG CLK_BUFG(
.I (DCM2_CLK),
.O (DIN_CLK)
);
endmodule[/code]
各位达人们,我想请问一下:XILINX中DCM部分？？那么用Altera的板子，PLL该怎么实现啊 ？？ 尤其是 .CLKIN_IBUFG_OUT(clk_reg) 这个怎么解释啊 ？看不懂啊 ？ 这个在Altera板子上怎么实线 ？？感谢，万分感谢。小弟在做论文啊...OFDM系统
