关于verilog HDL综合中的错误

    我之前学了VHDL，现利用暑假时间打算自学verilog HDL语言，刚刚开始就出现了问题，现将程序跟错误贴上，希望知道的各位大侠们能指点指点，谢谢·

 程序： `timescale 10ns/1ns
module wave1;
reg wave;
parameter cycle=10;
initial
  begin
               wave=0;
    #(cycle/2) wave=1;
    #(cycle/2) wave=0;
    #(cycle/2) wave=1;
    #(cycle/2) wave=0;
    #(cycle/2) wave=1;
    #(cycle/2) $finish;
  end
initial $monitor($time,,,"wave=%b",wave);
endmodule

错误：Error: Can't synthesize current design -- Top partition does not contain any logic