DAC0832是常用的8位DA转换芯片，建立时间为1us，用verilog硬件描述语言控制如下：
//name : ADC_0832
//author : qin wei he;
//date :2011.04.30;
//function:
module DAC_0832(
input clk, //外部时钟输入50M
input reset, //复位
input[7:0]data_in, //8位数据输入
input EN, //使能，只保持一个时钟周期
output reg CS,//DA0832片选信号
output reg WR, //读入信号
output reg[7:0] data);//8位数据输出
reg[7:0]data_in_reg;
always @(posedge clk or negedge reset)//判断使能信号，锁存输入数据
if( ! reset ) data_in_reg<=0;
else if(EN) data_in_reg <= data_in_reg;
else data_in_reg <= data_in_reg;
reg[2:0]cnt1;
always @(posedge clk or negedge reset)////100NS计数
if( ! reset ) cnt1 <= 3'b0;
else begin
if(cnt1 == 3'd5) cnt1 <= 0;
else cnt1 <= cnt1+ 1'b1;
end
reg[3:0]cnt2;
always @(posedge clk or negedge reset)
if( ! reset ) cnt2 <= 4'b0;
else begin
if(cnt2== 4'd11) cnt2 <= 3'b0;
else if(cnt1 == 3'd5) cnt2 <= cnt2 + 1'b1;
else cnt2 <= cnt2;
end
always @(posedge clk or negedge reset)
if( ! reset ) begin
CS<=1'b1;
WR <=1'b1;
data<=8'b0;
end
else begin
case ( cnt2 )
1,2,3,4,5,6,7,8, : begin CS <= 1'b0;end
default : CS <= 1'b1;
endcase
case (cnt2)
2,3,4,5,6,7 : begin WR <= 1'b0;end
default : WR <= 1'b1;
endcase
case (cnt2)
1 : data <= data_in_reg;
default : ;
endcase
end
endmodule
