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Lattice DCS (Dynamic Clock Select)

热度 2已有 257 次阅读2018-6-15 14:52 |个人分类:DCS| DCS

1、Why do I get a netsanitycheck PAR error when a MUX drives the clock of a IDDR/ODDR component? 
The netsanitycheck error indicates general routing is used to drive the IDDR and/or ODDR components. The logic must be modified to use dedicated clock resources:Solution 1: Do not use generic logic (e.g. MUX implemented by LUTs) to generate the clock for the IDDR/ODDR. The solution is to use a DCS for the MUX function instead. Solution 2: Use the dedicated clock routing resources when using a DCS. A typical application is to use the DCS to switch between a PLL input and PLL output clock. But beware, if a dedicated PLL input pin and the PLL CLKOS output are the two inputs of a DCS, the PLL input pin will go to the DCS via the general routing net. There are two possible work-arounds: A) Route the PLL input to the PLL’s CLKOK while bypassing the PLL. Then the CLKOS and the CLKOK PLL outputs can be connected to the DCS with the dedicated routing resource. b) Route the PLL input from a primary clock pin, not a PLL input pin. The PLL input and the CLKOS can be fed to the DCS directly without any problem. 
2、How to locate DCS in preference file for FPGA? 
DCS is a Digital clock select, a clock multiplexer, which is available in devices such as LatticeSC/M, LatticeXP2, LatticeECP2/M and LatticeECP3. 
How to assign DCS locations in .lpf preference file?The syntax is shown in the following example: LOCATE COMP “xxxx” SITE “DCSTB” ; The “xxxx” is the instantiation name in your VHDL or Verilog code. 
The DCS locations in LatticeSC family are at four edges – two per edge.DCSTA, DCSTBDCSLA, DCSLBDCSRA, DCSRBDCSBA, DCSBBwhere the letter right after “DCS” shows the edge the DCS is located: T is top, L is left, R is right, B is bottom. 
The DCS locations in LatticeXP2, LatticeECP2/M and LatticeECP3 families are near the Center Switch Box – two per quadrant.ULDCS1, ULDCS0URDCS1, URDCS0LLDCS1, LLDCS0LRDCS1, LRDCS0where UL is upper-left, UR is upper-right, LL is lower-left, LR is lower-right. These examples (in VHDL or Verilog) can be found in apps note for those devices that has DCS available. Here is one for XP2, ECP2/M and ECP3 in Verilog: 
DCS dcs_inst (.CLK1(DCS_clkin1), .CLK0(DCS_clkin0), .SEL(DCS_sel), .DCSOUT(DCS_clkout)); 
In the preference file, you can assign its location like this: 
LOCATE COMP “dcs_inst” SITE “LLDCS0” ; 
3、How do I determine the delay of a LaticeECP3 DCS cell from a Place and Route TRACE Report? 
A DCS (Dynamic Clock Select) element only drives primary clock nets.That is why the DCS cell delay is not presented by itself in a Place and Route TRACE Report.A TRACE report will show a 0 delay through the DCS cell.Instead, the sum of the DCS and and primary clock network delay is lumped as a whole into the DCS http://www.china-dcs.net/  output clock net delay in the TRACE report.Below is an example from a TRACE report, where the DCS cell delay (MUX_DEL) is 0 and the total cell and route delay is lumped into the global clock (ROUTE):Name Fanout Delay (ns) Site ResourcePADI_DEL — 0.457 C12.PAD to C12.PADDI clk0ROUTE 1 0.870 C12.PADDI to ULDCS0.CLK0 clk0_cMUX_DEL — 0.000 ULDCS0.CLK0 to ULDCS0.DCSOUT DCSInst0ROUTE 4 0.474 ULDCS0.DCSOUT to IOL_T2A.CLK dcsout_inferred_clock——–1.801 (25.4% logic, 74.6% route), 2 logic levels. 
4、How do I get the Lattice FPGA DCS to switch from an inactive clock to an active one in simulation? 
DCS is a global clock buffer incorporating a smart multiplexer function that takes two independent input clock sources and avoids glitches or runt pulses on the output clock, regardless of where the enable signal is toggled. When selection input is toggled, the DCS looks for the current clock waveform as well as the new clock waveform. When one clock input is not operating, the simulation will not work because there is no current clock wave for information. The hardware will switch from in-operative clock to working clock eventually but may suffer additional delay for DCS output to settle down to active clock. If user must switch between inactive clock and active clock, regular mux must be used. Refer to Lattice Technical note, TN1178: LatticeECP3 sysCLOCK/PLL Design and Usage Guide. It is available at the link below. 

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回复 eric_wang 2018-6-17 13:33
这是哦什么
回复 3228 2018-6-17 13:37

facelist doodle 涂鸦板

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